Graf Research Presents "Measuring Trust" at MAPLD 2018

For a second consecutive year, Graf Research has been invited to the Military and Aerospace Programmable Logic Devices (MAPLD) Workshop in La Jolla, Califrnia to present our work on trusted microelectronics.  Jonathan Graf will present a topic entitled "Measuring Trust" on May 24.  Be sure to stop in and see our presentation!

Measuring Trust

By Jonathan Graf

MAPLD 2018

In space and defense microelectronics research, we often define trust in a domain-specific manner: we trust our microelectronic devices when they are genuine devices that do what they are supposed to do and nothing else.   Measuring whether a microelectronic device is trusted requires blending disparate contributors.  In practice, however, many tend to focus on one contributor to the exclusion of others.  We often look exclusively at trust assessment methods (tools, best practices, techniques) that measure attributes of systems or devices, conflating a measurement of method efficacy with a measure of trust.  How to transition from metrics that measure the efficacy of a method to metrics that measure all components that contribute to trust is an ongoing topic of research, both at Graf Research and elsewhere.  These trust metrics systems blend measurements of methods with the concept of an adversary.  The adversary has their own methods and uses them to interact with a defender in an engagement.  Modeling this engagement correctly requires knowledge not only of the strategies available to each party but also their resources, capabilities, and goals.  A useful model that considers all these elements can quantitatively inform those who wish to measure whether their devices meet the above trust definition.

In this invited talk, we will construct a system of trust metrics that considers all requisite elements.  It uses a quantified, cost-indexed risk function as a trust metric to describe the payoff to a defender for selecting certain sets of methods as a detection strategy.  It similarly models the adversary and their payoff for selecting an exploitation strategy.  The goal of each party is to maximize their payoff.  We demonstrate how these two payoff metrics may be combined using game theory to select the optimal strategies for both the adversary and defender to achieve their highest payoff when considering the likely actions of the other party.  This example system focuses on hardware Trojan detection.  It tells the defender the optimal method of how to find Trojans. Incidentally, it also tells the adversary the optimal methods of how to exploit the system.  We conclude the talk by comparing this metric to other emerging trust metrics.

Graf Research at IEEE HOST (and TAME and WISE)

Graf Research will be at the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) as well as the co-located workshops the Trusted and Assured MicroElectronics Forum (TAME) and Women in Hardware and Systems Security (WISE).   Please say hello to Jonathan Graf, who will be a poster session chair and judge at HOST and a panelist in the TAME forum, and Whitney Batchelor, who will be a poster judge at WISE.  See you there!


Graf Research Becomes Xilinx Alliance Program Member

After two years as a Xilinx Alliance Program Associate, Graf Research has upgraded our status in the Xilinx Alliance Program to the "Member" level!  Xilinx examined our quality, business, and technical practices through a self-audit we submitted in order to meet the corporate requirements for membership.  Xilinx further trained our staff to be certified as proficient and knowledgeable in the latest Xilinx technologies.  

As we continue to collaborate with Xilinx and make use of their technologies, we are pleased to take this step in our relationship.

Graf Research at GOMAC 2018

Scott Harper from Graf Research will be attending GOMAC 2018 in Miami from March 12-15.  Our very own Scott Harper and Tim Dunham are co-authors on "Malicious Trigger Discovery in FPGA Firmware."  Make sure to say hello to Scott!

Graf Research Awarded SBIR: "Optimal 3rd-Party IP Assessment"

Graf Research has been awarded an SBIR to produce one or more ASIC and FPGA hardware 3rd-Party IP (3PIP) assessment techniques, a set of technologies we collectively refer to as GR-3PIP. The techniques must accomplish the goal of establishing trust in the 3PIP under test, but we apply additional requirements. We require that the techniques (1) do not add significant cost to the core, (2) do not require extensive time to apply, and (3) do not require extensive verification or reverse engineering expertise to use.


XSWG 2017: "Irrefutable Tamper Logging through FPGA Key Management"

Graf Research will be presenting our work on “Irrefutable Tamper Logging through FPGA Key Management” at both US Xilinx Security Working Groups: Longmont, Colorado (Oct 17-19) and Herndon, Virginia (Nov 7-9).   Co-authors include Jonathan Graf and Ali Asgar Sohanghpurwala from Graf Research and Matthew French and Dr. Andrew Schmidt from USC-ISI.  Register for the conference and come see us!

Graf Research Awarded Contract to Interface OpTrust Tools

Graf Research has been awarded a contract to create interfaces between our OpTrust software, which creates game-theory-based prescriptions for optimal hardware Trojan detection, and a prime contractor's custom electronic design automation tools. 

IEEE NAECON 2017: "Formal Enforcement of Mission Assurance Properties in Cyber-Physical Systems"

Graf Research and Georgia Tech are publishing and presenting our research on "Formal Enforcement of Mission Assurance Properties in Cyber-Physical Systems" at IEEE NAECON 2017.  Come out and see our presentation!

Formal Enforcement of Mission Assurance Properties in Cyber-Physical Systems
Scott Harper, Jonathan Graf, Michael A. Capone, Justin Eng, Michael Farrell, Lee W. Lerner

Abstract— Cyber-Physical Systems improve efficiency, accuracy, and access in systems ranging from household appliances to power stations to airplanes. They also bring new risks at the intersection of physical, information, and mission assurance. This paper presents CP-SMARTS, a framework providing a means for propagating CPS assurances from planning to deployment.

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SEE/MAPLD 2017 Invited Lecture: "Optimizing Forward Design Trust for FPGAs"

Jonathan Graf will present an invited lecture on "Optimizing Forward Design Trust for FPGAs" at the 2017 Single Event Effects Symposium / Military and Aerospace Programmable Logic Devices Workshop in San Diego on May 25.  Come on out and see us!

Optimizing Forward Design Trust for FPGAs

Jonathan Graf

Abstract: Graf Research Corporation is developing a workflow to enable optimal forward design trust for Field Programmable Gate Arrays.  This flow is enabled by a blend of commercial EDA software, Graf Research specialized tools and techniques, and, as needed, custom trust analysis tools and techniques.  Custom tools include PV-Bit, which bridges the current gap between a trusted gate level netlist and the FPGA bitstream, bringing trust all the way into the bitstream.  To develop a trusted gate-level netlist, other trust analysis techniques must have preceded the use of PV-Bit.  The Graf Research contribution during synthesis, map, place, and route steps, is a tool called OpTrust, which uses a game theoretic decision engine to prescribe the optimal set of tests for the trust analysis of a design based on current threat data, the criticality of the design, and the availability of commercial verification or custom hardware Trojan detection methods.  Another element of trusted design is trusting the 3rd-Party IP cores present in the design.  The end goal of this assessment flow is to put the trust analysis of FPGA designs within the reach of the FPGA developer.  That is, we wish to ensure that the developer might perform the trust analysis themselves, pushing trust forward as each step in the design process is completed, concluding with a trusted bitstream.