Viewing entries in
Invited Lecture

Graf Research Presents "Measuring Trust" at MAPLD 2018

For a second consecutive year, Graf Research has been invited to the Military and Aerospace Programmable Logic Devices (MAPLD) Workshop in La Jolla, Califrnia to present our work on trusted microelectronics.  Jonathan Graf will present a topic entitled "Measuring Trust" on May 24.  Be sure to stop in and see our presentation!

Measuring Trust

By Jonathan Graf

MAPLD 2018

In space and defense microelectronics research, we often define trust in a domain-specific manner: we trust our microelectronic devices when they are genuine devices that do what they are supposed to do and nothing else.   Measuring whether a microelectronic device is trusted requires blending disparate contributors.  In practice, however, many tend to focus on one contributor to the exclusion of others.  We often look exclusively at trust assessment methods (tools, best practices, techniques) that measure attributes of systems or devices, conflating a measurement of method efficacy with a measure of trust.  How to transition from metrics that measure the efficacy of a method to metrics that measure all components that contribute to trust is an ongoing topic of research, both at Graf Research and elsewhere.  These trust metrics systems blend measurements of methods with the concept of an adversary.  The adversary has their own methods and uses them to interact with a defender in an engagement.  Modeling this engagement correctly requires knowledge not only of the strategies available to each party but also their resources, capabilities, and goals.  A useful model that considers all these elements can quantitatively inform those who wish to measure whether their devices meet the above trust definition.

In this invited talk, we will construct a system of trust metrics that considers all requisite elements.  It uses a quantified, cost-indexed risk function as a trust metric to describe the payoff to a defender for selecting certain sets of methods as a detection strategy.  It similarly models the adversary and their payoff for selecting an exploitation strategy.  The goal of each party is to maximize their payoff.  We demonstrate how these two payoff metrics may be combined using game theory to select the optimal strategies for both the adversary and defender to achieve their highest payoff when considering the likely actions of the other party.  This example system focuses on hardware Trojan detection.  It tells the defender the optimal method of how to find Trojans. Incidentally, it also tells the adversary the optimal methods of how to exploit the system.  We conclude the talk by comparing this metric to other emerging trust metrics.

Graf Research at IEEE HOST (and TAME and WISE)

Graf Research will be at the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) as well as the co-located workshops the Trusted and Assured MicroElectronics Forum (TAME) and Women in Hardware and Systems Security (WISE).   Please say hello to Jonathan Graf, who will be a poster session chair and judge at HOST and a panelist in the TAME forum, and Whitney Batchelor, who will be a poster judge at WISE.  See you there!

 

SEE/MAPLD 2017 Invited Lecture: "Optimizing Forward Design Trust for FPGAs"

Jonathan Graf will present an invited lecture on "Optimizing Forward Design Trust for FPGAs" at the 2017 Single Event Effects Symposium / Military and Aerospace Programmable Logic Devices Workshop in San Diego on May 25.  Come on out and see us!

Optimizing Forward Design Trust for FPGAs

Jonathan Graf

Abstract: Graf Research Corporation is developing a workflow to enable optimal forward design trust for Field Programmable Gate Arrays.  This flow is enabled by a blend of commercial EDA software, Graf Research specialized tools and techniques, and, as needed, custom trust analysis tools and techniques.  Custom tools include PV-Bit, which bridges the current gap between a trusted gate level netlist and the FPGA bitstream, bringing trust all the way into the bitstream.  To develop a trusted gate-level netlist, other trust analysis techniques must have preceded the use of PV-Bit.  The Graf Research contribution during synthesis, map, place, and route steps, is a tool called OpTrust, which uses a game theoretic decision engine to prescribe the optimal set of tests for the trust analysis of a design based on current threat data, the criticality of the design, and the availability of commercial verification or custom hardware Trojan detection methods.  Another element of trusted design is trusting the 3rd-Party IP cores present in the design.  The end goal of this assessment flow is to put the trust analysis of FPGA designs within the reach of the FPGA developer.  That is, we wish to ensure that the developer might perform the trust analysis themselves, pushing trust forward as each step in the design process is completed, concluding with a trusted bitstream.

Jonathan Graf Invited Talk at Virginia Tech CESCA

Jonathan Graf of Graf Research along with co-presenter Dale Reese of Idaho Scientific will be giving an invited lecture to Virginia Tech's Center for Embedded Systems for Critical Applications (CESCA)The topic is "FPGA MPSoC Security: Design and Runtime."  Come on out and hear us!  Details below:

FPGA MPSoC Security: Design and Runtime

Jonathan Graf, Founder, Graf Research; Dale Reese, Founder and Chief Scientist, Idaho Scientific

2:30pm - 3:30pm on April 15, 2016 (Friday) at Whittemore Hall 457

Abstract:   An emerging class of Field Programmable Gate Array (FPGA) – the Multi-Processor System on Chip (MPSoC) – holds enormous promise for novel processing architectures in a variety of domains. Within the context of high-security systems, the same-die close coupling of heterogeneous processing structures with hardened security resources is of particular interest. Modern FPGA MPSoCs provide not only programmable FPGA fabric, ARM CPUs, graphics processor units (GPUs), and digital signal processors (DSPs) but also cryptographic accelerators, physically unclonable functions (PUFs), and hardware random number generators (HRNGs). This pairing of processing and security resources raises the possibility of using them to create tightly integrated, custom secure processors for emerging networked applications that demand the highest security standards. FPGA MPSoCs hold the potential of revolutionizing the security posture for high-security Internet of Things (IoT) applications such as autonomous vehicles, intelligent energy grid devices, home and industrial automation, cyber-physical systems – and even the datacenter.

In this seminar, Jonathan Graf (Graf Research) and Dale Reese (Idaho Scientific) will introduce the variety of embedded computing security disciplines that meet within the confines of FPGA MPSoCs. Security must be built into these devices from the moment they are first designed, all the way through their supply chains, during the development of each piece of software and firmware, and throughout every runtime operation of each disparate processing structure. Collectively, this makes the FPGA MPSoC an exciting new device class with exceptional opportunities for new embedded computing security innovation.

150 VT Logo.jpg