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GOMAC 2023 - Booth and Session Information

GOMAC 2023 - Booth and Session Information

Come see our presentations, posters, and booth at GOMAC 2023! Click here for the full GOMAC 2023 program schedule.

Poster Session: The poster session is at 10:30am – 12:10pm, Thurs March 23. We hope to see you there!

  • Poster P50-38: “Generating Statistically Relevant Trojan Benchmarks for Microelectronics Quantifiable Assurance”

  • Poster P50-39: “Facilitating Assurance and Collaboration through Digital Threads in Microelectronics Experiments”

Presentation Session: We’re presenting our third paper in Session 38: Side-Channel Analysis, at 1:30 – 3:10pm, Thurs March 23.

  • Session 38-5: “Determining Residual Risk from Optimized Selection of Hardware Trojan Detection Strategies”

We will also be present in the ongoing Exhibits session at Booth 713 where you can talk to our experts about the software tools we offer, including Enverite design assurance solutions and our OpTrust service. We’ll be available at our booth all day on Tues March 21 and Wed March 22.

GOMAC 2023 - Three Papers

GOMAC 2023 - Three Papers

We’re presenting three papers at GOMAC 2023 in March – two posters and one presentation. Our papers discuss the quality of trojan benchmarks for microelectronics quantifiable assurance as well as a methodology for calculating the risk in hardware trojan detection strategies. We are also discussing our microelectronics lab experimentation platform, Benches, and how it can be used to capture digital threads of experiments. We will be demoing Benches at our booth, so definitely come check that out!

We’ll send out another update soon with information on our session numbers and dates. The team has put in significant effort, and we can’t wait for you to see it.


Poster

Generating Statistically Relevant Trojan Benchmarks for Microelectronics Quantifiable Assurance

Margaret Winslow, Whitney Bachelor, James Koiner, Kevin Paar, Scott Harper, Jonathan Graf

Abstract: Hardware trojan horse (HTH) detection metrics are used to quantify the value of trojan detection methods. These metrics, often in terms of probability of detection and probability of false alarm, can be used to help quantify the impact on design assurance when applying mitigations to a microelectronics circuit. A question arises, however, regarding how statistically sound the metric values must be to make reasonable trust and assurance decisions. Statistical relevance metrics have been used in many fields to justify confidence in claims, and benchmarks that can produce statistically relevant detection metrics are necessary to trust the quantification of microelectronics assurance. This work defines the requirements for generating statistically relevant detection metrics that are useful for quantifying microelectronics design assurance via testing with a strategically implemented circuit design benchmark set.

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Presentation

Determining Residual Risk from Optimized Selection of Hardware Trojan Detection Strategies

Zachary A. Collier, Whitney Batchelor, Margaret Winslow, Scott Harper, Jonathan Graf

Abstract: Game theory has been shown to have practical applications in the optimal selection of hardware trojan detection and prevention strategies for circuit design. Previous work has used quantitative metrics measuring performance and cost of a countermeasure to predict optimal defense strategy selections, while considering the goals and actions of an adversary. This was accomplished with a game theoretic model of the response of a defender and an attacker to possible design assurance strategy selections. To date, no concrete quantification of the changes in risk associated with the resulting design decisions has been presented. This work introduces a methodology for deriving and calculating the inherent risk, residual risk, and risk reduction that result from the game theoretic models of design decisions when evaluating hardware trojan detection and prevention strategies.

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Poster

Facilitating Assurance and Collaboration through Digital Threads in Microelectronics Experiments

Edward Carlisle IV, Scott Harper, Jonathan Graf

Abstract: Laboratory experimentation with circuits and systems can be a complex process. Exact repetition of processes such as radiation testing, second-party verification of conclusions drawn from side channel analysis, and preservation of experimental processes all require the full detail of an experiment to be captured when it is run. Capturing a digital thread of an experiment provides this capability but can be a complex process that is prone to human error if not fully automated. This paper presents an automated microelectronics lab experimentation platform called Benches. We describe how Benches automates the capture of the digital thread of a microelectronics experiment and how these digital threads facilitate assurance and collaboration.

Graf Research at GOMAC 2018

Scott Harper from Graf Research will be attending GOMAC 2018 in Miami from March 12-15.  Our very own Scott Harper and Tim Dunham are co-authors on "Malicious Trigger Discovery in FPGA Firmware."  Make sure to say hello to Scott!