Jonathan Graf will present an invited lecture on "Optimizing Forward Design Trust for FPGAs" at the 2017 Single Event Effects Symposium / Military and Aerospace Programmable Logic Devices Workshop in San Diego on May 25. Come on out and see us!
Optimizing Forward Design Trust for FPGAs
Abstract: Graf Research Corporation is developing a workflow to enable optimal forward design trust for Field Programmable Gate Arrays. This flow is enabled by a blend of commercial EDA software, Graf Research specialized tools and techniques, and, as needed, custom trust analysis tools and techniques. Custom tools include PV-Bit, which bridges the current gap between a trusted gate level netlist and the FPGA bitstream, bringing trust all the way into the bitstream. To develop a trusted gate-level netlist, other trust analysis techniques must have preceded the use of PV-Bit. The Graf Research contribution during synthesis, map, place, and route steps, is a tool called OpTrust, which uses a game theoretic decision engine to prescribe the optimal set of tests for the trust analysis of a design based on current threat data, the criticality of the design, and the availability of commercial verification or custom hardware Trojan detection methods. Another element of trusted design is trusting the 3rd-Party IP cores present in the design. The end goal of this assessment flow is to put the trust analysis of FPGA designs within the reach of the FPGA developer. That is, we wish to ensure that the developer might perform the trust analysis themselves, pushing trust forward as each step in the design process is completed, concluding with a trusted bitstream.