PAINE 2026

• F. Archuleta, J. Koiner, A.A. Sohanghpurwala, W. Batchelor, J. Graf, S. Harper, "Composing HTH Benchmarks for Evaluating Bitstream-level Detection Methods," IEEE Physical Assurance and Inspection of Electronics (PAINE) Conf., October 2026.

ITC 2026

• F. Archuleta, J. Koiner, A.A. Sohanghpurwala, W. Batchelor, J. Graf, S. Harper, "Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods," International Test Conference (ITC), October 2026.

DASC 2026

• A. A. Sohanghpurwala, J. Graf, S. Harper, M. Winslow, E. Drinkert, "Accelerating FPGA-Based Avionics System Recertification with Bitstream-Level Verification of Physical Isolation and Delta Verification Methodologies," Digital Avionics Systems Conference (DASC), September 2026.

Anti-Tamper Conference 2026

• W.  Batchelor, "Accelerating Netlist Reverse Engineering with Agentic AI," DoD Anti-Tamper Conference, April 2026.

• K. Paar, S. Harper, "Anti-Tamper Implementation: A Framework for Complete Zeroization of AMD Versal SoC Based Systems," DoD Anti-Tamper Conference, April 2026.

• S. Harper, A. Cook, B. Ladd, J. Graf, "Forge: A Security Lifecycle Manager for FPGAs," DoD Anti-Tamper Conference, April 2026.

GOMAC 2026

• W. Batchelor, M. Winslow, C. Crofford, C. Fraley, K. Paar, S. Harper, "Accelerating Netlist Reverse Engineering with Artificial Intelligence," GOMACTech 2026 Proceedings, March 2026.

• A.A. Sohanghpurwala, S. Harper, J. Graf, M. Winslow, W. Batchelor, T. Dunham, "Bitstream-level verification of Physical Isolation with PV-Bit," GOMACTech 2026 Proceedings, March 2026. Link to PDF.

SecDev 2025

• A.A. Sohanghpurwala, D. Gibson, S. Harper, J. Graf, T. Dunham, "PV-Bit: Private Verification of FPGA Bitstreams Via Bitstream Equivalence Checking," IEEE Secure Development Conference (SecDev), Oct. 14-16, 2025.

DASC 2025

• J. Graf, E. Drinkert, S. Harper, M. Winslow, A. Cook, A.A. Sohanghpurwala, T. Dunham, W. Tabada, "Accelerating Recertification of FPGA-Based Avionics Systems via Bitstream Equivalence Checking," Digital Avionics Systems Conference (DASC), Sept. 14-18, 2025.

SAE Technical Papers 2025

• W. Batchelor, C. Crofford, J. Koiner, M. Winslow, M. Taylor, K. Paar, S. Harper, "Counterfeit FPGA Characterization and Detection with Soft Sensors and Machine Learning," SAE Technical Paper 2025-01-0457, 2025, https://saemobilus.sae.org/papers/counterfeit-fpga-characterization-detection-soft-sensors-and-machine-learning-2025-01-0457.

GOMAC 2025

• W. Batchelor, C. Crofford, M. Winslow, M. Taylor, K. Paar, J. Koiner, S. Harper, “Towards Synthetic Data Generation for Characterization of FPGAs,” GOMACTech 2025 Proceedings, March 2025. Link to PDF.

• E. Carlisle, J. Koiner, E. Ezell, S. Harper, “System-Level Fault Injection on Heterogeneous System-on-Chips,” GOMACTech 2025 Proceedings, March 2025. Link to PDF.

• J. Graf, M. Winslow, E. Drinkert, K. Urish, J. Hallman, “FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking,” GOMACTech 2025 Proceedings, March 2025. Link to PDF.

PAINE 2024

• E. Carlisle, S. Harper, J. Graf, “Improving Workforce Development with Laboratory Automation,” 2024 IEEE Physical Assurance and Inspection of Electronics (PAINE) Conf., Nov. 12-14, 2024.

GVSETS 2024

• K. Paar, S. Harper, “Challenges and Mitigations for Data Remanence in FPGA Based Systems,” Ground Vehicle Systems and Technology Symposium (GVSETS), Aug 2024. Link to PDF.

ICMLCN 2024

• S. Adams, M. Taylor, C. Crofford, S. Harper, W. Batchelor, W. Headley, “Exploring Explainable AI Techniques for Radio Frequency Machine Learning,” IEEE International Conference on Machine Learning for Communication and Networking (ICMLCN), May 2024. Link to paper.

Anti-Tamper Conference 2024

• “Automating Hardware Trojan Insertion for Producing a Trusted & Assured Microelectronics Benchmark Dataset,” J. Koiner, K. Paar, M. Blacconiere, M. Winslow, S. Harper, J. Graf, DoD Anti-Tamper Conference, April 2024.

GOMAC 2024

• “The Role of EDA in FPGA Assurance Best Practices,” M. Winslow, J. Graf, W. Batchelor, S. Harper, K. Paar, A.A. Sohanghpurwala,  GOMACTech 2024, March 2024. Link to PDF.

• “Non-Destructive Evaluation of Repackaged Counterfeit FPGAs via Machine Learning,” W. Batchelor, J. Koiner, C. Crofford, K. Paar, M. Winslow, M. Taylor, S. Harper, GOMACTech 2024, March 2024. Link to PDF.

PAINE 2023

• “Attest: Non-Destructive Identification of Counterfeit FPGA Devices,” W. Batchelor, J. Koiner, C. Crofford, K. Paar, M. Winslow, M. Taylor, S. Harper, IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), Oct 2023. Link to paper.

GOMAC 2023

• "Generating Statistically Relevant Trojan Benchmarks for Microelectronics Quantifiable Assurance," M. Winslow, W. Batchelor, J. Koiner, K. Paar, S. Harper, and J. Graf, GOMAC 2023. Link to PDF.

• "Determining Residual Risk from Optimized Selection of Hardware Trojan Detection Strategies," Z. A. Collier, W. Batchelor, M. Winslow, S. Harper, and J. Graf, GOMAC 2023. Link to PDF.

• "Facilitating Assurance and Collaboration through Digital Threads in Microelectronics Experiments," E. Carlisle IV, S. Harper, and J. Graf, GOMAC 2023. Link to PDF.

Anti-Tamper Conference 2022

• “Anti-Tamper Implementation – An Irrefutable Logger in Microchip Polarfire Devices,” K. Paar, J. Graf, S. Harper, and T. Dunham, DoD Anti-Tamper Conference 2022.

• “Modernizing FPGA Design Assurance Software,” J. Graf, S. Harper, A. A. Sohanghpurwala, and E. Carlisle, DoD Anti-Tamper Conference 2022.

GOMAC 2022

• “Modernizing FPGA Design Assurance Software,” J. Graf, S. Harper, A. A. Sohanghpurwala, and E. Carlisle, GOMAC 2022. Link to PDF.

• “Advancing Strategy Selection for Hardware Trojan Detection with Subrational Behavior Models,” W. Batchelor, M. Winslow, C. Crofford, M. Blacconiere, S. Harper, J. Graf, GOMAC 2022. Link to PDF.

• “Trace: Towards a Traceable Microelectronics Implementation Flow,” A. A. Sohanghpurwala, C. Fraley, J. Graf, S. Harper, GOMAC 2022. Link to PDF.

• “Automated Analysis of a Thermally Triggered FPGA Hardware Trojan,” E. Carlisle, S. Harper, J. Koiner, K. Paar, M. Capone, and J. Graf, GOMAC 2022. Link to PDF.

GOMAC 2021

• “GameRunner: Automating Analysis and Optimization of Microelectronics Trust with Game Theory,” E. Carlisle, J. Graf, W. Batchelor, S. Harper, GOMAC 2021. Link to PDF.

• “IP Integrity Flow: Ensuring IP Integrity in FPGA Synthesis,” A. A. Sohanghpurwala, C. Fraley, S. Harper, J. Graf, A. Cook, T. Dunham, GOMAC 2021. Link to PDF.

• “DELV: Datasheet/English to Logic Verification,” E. Carlisle, J. Koiner, S. Frederiksen, J. Graf, S. Harper, J. Aromando, and M. Hsiao, GOMAC 2021. Link to PDF.

HaSS Journal 2019

• “A practical application of game theory to optimize selection of hardware Trojan detection strategies,” J. Graf, W. Batchelor, S. Harper, R. Marlow, E. Carlisle, and P. Athanas, HaSS Journal, December 2019. Link to Springer website.

GOMAC 2019

• “Introducing a Trust Metric Foundation and Deriving Trust-for-Buck,” S. Harper, J. Graf, W. Batchelor, T. Dunham, and P. Athanas, GOMAC 2019. Link to PDF.

NAECON 2018

• "Hardware Trojan Detection using Xilinx Vivado", R. Marlow, S. Harper, W. Batchelor, J. Graf, in IEEE National Aerospace and Electronics Conference (NAECON), July 2018. Link to PDF.

NAECON 2017

• “Formal Enforcement of Mission Assurance Properties in Cyber-Physical Systems,” S. Harper, J. Graf, M.A. Capone, J. Eng, M. Farrell, L.W. Lerner, in IEEE National Aerospace & Electronics Conference (NAECON), June 2017. Link to PDF.

Anti-Tamper Conference 2017

• “Irrefutable Tamper Logging through FPGA Key Management,” J. Graf, A. A. Sohanghpurwala, M. French, and A. Schmidt, in DoD AT Conference Proceedings, April 2017.

GOMAC 2017

• “Private Verification for FPGA Bitstreams,” J. Graf and A. A. Sohanghpurwala, in GOMACTech 2017 Proceedings, March 2017. Link to PDF.

• “OpTrust: Software for Determining Optimal Test Coverage and Strategies for Trust,” J. Graf, in GOMACTech 2017 Proceedings, March 2017. Link to PDF.

NAECON 2016

• “Towards System-Level Adversary Attack Surface Modeling for Microelectronics Trust,” J. Graf, in IEEE National Aerospace and Electronics Conference (NAECON), July 2016. Link to PDF.

HOST 2016

• “Trust Games: How Game Theory Can Guide the Development of Hardware Trojan Detection Methods,” J. Graf, in Hardware Oriented Security and Trust (HOST), 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2016. Link to PDF.

GOMAC 2016

• “Toward Optimal Hardware Trojan Detection through Security Economics and Game Theory,” J. Graf, in GOMACTech 2016 Proceedings, March 2016, paper 14.4. Link to PDF.

Leadership

Jonathan Graf, PhD

CEO and Founder

Jon is the founder and CEO of Graf Research, where he leads research and product development in FPGA security, microelectronics trust, and assurance-focused electronic design automation. He has a deep expertise in FPGA (Field Programmable Gate Array) design and security. At Graf Research, his team focuses on innovations like the Enverité EDA suite, which verifies FPGA bitstreams and secures FPGA build flows. His technical work has helped define several threads of modern FPGA assurance, including game-theoretic and security-economic methods for selecting hardware Trojan detection strategies, private verification of FPGA bitstreams through PV-Bit, and numerous FPGA technologies for design, security, and assurance.

Alan Cook

Enverité Product Manager​

Alan is the Product Manager for Enverité EDA, bringing more than 20 years of experience in the commercial software industry. He oversees the delivery of high-quality products and solutions, ensuring they align with customer needs and evolving market demands.​

Scott Harper, PhD

CTO

Scott has a long history of defining and implementing unique solutions to challenging problems, bringing over 30 years of FPGA R&D experience in design and tooling to his current role as CTO of Graf Research Corporation. At GRC, he is focused on both identification of approaches to address assurance gaps in microelectronics design flows and the production of EDA tools that aid developers in ensuring their FPGA system security and safety goals are met from design through to the bitstream.​

ALI ASGAR SOHANGHPURWALA, PhD​

Principal Research Engineer

Ali is a Principal Research Engineer at Graf Research Corporation (GRC), where he serves as Principal Investigator on R&D efforts in FPGA design assurance, security, and reliability. A coinventor of Enverité PV-Bit and Enverité Trace, he brings nearly 20 years of experience in developing custom EDA capabilities and creating hardware and software solutions for embedded microelectronics applications.

Whitney Batchelor

Director of Research

Whitney is a mathematician and the Director of Research for Graf Research. She has 14 years of experience working in microelectronics trust and assurance spanning projects across DoD and Industry. Since starting at Graf Research, she has served as the PI for over 15 research programs across DoD with an emphasis on applying mathematics in novel ways to solve assurance challenges. In addition to overseeing all of the current research at Graf Research, her immediate work has recently been focused on AI assurance, systems engineering for assurance, applied AI/ML, and quantifiable, evidence-based methods for FPGA assurance and security. ​

Tim Dunham

Principal Software Engineer

Tim is a Principal Software Engineer and chief architect for Enverité PV-Bit. His work includes hardware design, software to interpret and raise the abstraction of hardware designs, and custom user interfaces to intuitively present a variety of complex underlying operations. His flexibility has been integral to the success of multiple Graf Research projects.

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