Starting Friday, November 7th, we invite veterans and their loved ones to stop by Moon Hollow Brewing to enjoy a drink on us. Thank you, veterans.
Graf Research is proud to announce that Dr. Ali Asgar Sohanghpurwala will present at IEEE SecDev 2025 on “PV-Bit: Private Verification of FPGA Bitstreams Via Bitstream Equivalence Checking.”
This talk will explore the theory and practice of private verification, showing how PV-Bit enables organizations to confirm bitstream equivalence without exposing sensitive design details. Dr. Sohanghpurwala will detail how we evaluated PV-Bit against an open-source design set for both false positives in unmodified designs and accurate detection for designs with fault injections.
PV-Bit represents a key advance in protecting both intellectual property and mission-critical systems. We look forward to sharing our latest research with the SecDev community and advancing the state of practice in secure hardware design.
PV-Bit: Private Verification of FPGA Bitstreams Via Bitstream Equivalence Checking
Ali Asgar Sohanghpurwala, Daniel Gibson, Scott Harper, Jonathan Graf, Timothy Dunham
Established FPGA design verification flows utilize sophisticated methods to provide assurance for microelectronic designs deployed on FPGA based systems, but they lack visibility into the vendor proprietary configuration bitstream format. This means the assurances they provide only extend as far as the post place and route simulation netlist, leaving a verification gap where errors or malicious modifications could be introduced during the bitstream generation process. Here, we discuss and evaluate the operation and efficacy of PV-Bit as a tool that can address this gap via Bitstream Equivalence Checking: proving physical (and thus functional) equivalence between the bitstream and a verified, trusted netlist. PV-Bit uniquely performs this check without exposing private Intellectual Property included in the bitstream.
At the upcoming AMD Security Working Group, Graf Research will share our latest contributions to advancing FPGA security and assurance.
Our joint presentation with AMD, “Isolation Design Flow / Verifying Isolation at the Bitstream Level”, will demonstrate how engineers can design with confidence by validating critical isolation properties in the FPGA bitstream. We will also introduce the Forge Security Lifecycle Manager, a new tool that streamlines assurance throughout the hardware development process.
Beyond our technical sessions, we are excited to connect with partners and colleagues during Partner Night, where we’ll discuss the broader Enverite suite and its role in strengthening the FPGA security ecosystem. Don’t miss this opportunity to engaging in meaningful collaboration with the wider security and semiconductor community.
Longmont, CO, from October 14 – 15, 2025
Washington, D.C., from November 5 – 6, 2025
Munich, Germany, from December 9 – 10, 2025
For more information, visit https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/design-security.html#security-working-group
Graf Research is proud to share that our Director of Research, Whitney Batchelor, is presenting at PAINE 2025. Her talk, “Mathematical Approaches to Microelectronics Assurance,” will highlight how mathematics is not just a supporting tool but a core element in addressing assurance challenges in microelectronics. Whitney will demonstrate how a deeper mathematical perspective enables stronger, more reliable methods for ensuring trust in microelectronic systems. We look forward to Whitney’s vision setting the stage for important conversations at PAINE 2025.
Graf Research is excited to attend DASC 2025, where we will discuss the impact of Enverite PV-Bit on avionics safety. Be sure to visit our booth to learn more about how Enverite by Graf Research is helping shape the future of safety and security in FPGA-based avionics systems.
Accelerating Recertification of FPGA-Based Avionics Systems via Bitstream Equivalence Checking
Jonathan Graf, Evan Drinkert, Scott Harper, Margaret Winslow, Alan Cook, Ali Asgar Sohanghpurwala, Tim Dunham, and Wilfredo Tabada
Field programmable gate arrays (FPGAs) are ubiquitous in avionics. While FPGAs are easily reprogrammable, update cycles can be long even for minor changes due to recertification testing requirements. Formal verification software can provide proofs about some portions of the FPGA re-design process, but standard formal verification software cannot validate the final FPGA bitstream design. A new software technique, Bitstream Equivalence Checking (BEC), can prove the logical and physical equivalence of an FPGA bitstream to a physical netlist representation. Used in concert with Logic Equivalence Checking (LEC) as well as timing and physical design analysis tools, BEC enables a new delta verification flow that defines the relationship between an original, certified FPGA bitstream and the bitstream that results after minor updates to the source code. This paper explains the process and illustrates its application to an example AMD Xilinx FPGA design when modified with a variety of source changes. The consequences of applying the process to avionics systems recertification are explored.
Next week, Graf Research is heading to FPL 2025 with two talks and a demo showcasing our latest work in FPGA security. Dr. Jonathan Graf will be talking about “Securing Custom Computing Devices: Observations from the Lab and Market” at the SCCM workshop. Whitney Batchelor is presenting how Graf Research R&D efforts led to the development of our Enverite EDA suite. Lastly, at demo night, Dr. Graf will demonstrate how Enverite PV-Bit bitstream equivalence checking detects a Hardware Trojan directly inserted into a bitstream.
Learn more about the event: https://2025.fpl.org/
Join us as Dr. Jonathan Graf, CEO of Graf Research, presents a technical talk and demonstration of Enverite PV-Bit. Enverite PV-Bit extends equivalence checking into the bitstream, allowing users to verify that the deployed bitstream accurately represents the original design.
We’ll also be hosting a booth at the conference. Come speak directly with our engineers and discover how Enverite PV-Bit can streamline your verification process and improve the safety and security of your FPGA deployments. We’re looking forward to connecting with the FPGA community in Munich!
For more information about the conference, visit FPGA Conference Europe.
Graf Research will be at DAC in San Francisco, California, from June 23 - June 25. DAC is the premier event for design and automation in electronics. We’re excited to engage with engineers, researchers, and innovators shaping the future of microelectronic systems.
Visit us at booth 2128, where our engineering team will be providing demonstrations of the Enverite PV-Bit product. Bitstream equivalence checking with Enverite PV-Bit can augment your FPGA toolchain to increase the safety, security, and assurance of your system.
Learn more about DAC, the Design Automation Conference.
Graf Research is attending the AMD Premier Partner Summit 2025 in San Jose from June 17-19. This summit is always a great opportunity for learning, networking, and building meaningful technical partnerships. We are especially excited to highlight Enverite PV-Bit, our bitstream equivalence checking tool, and its applicability in safety- and security-critical fields. We look forward to joining fellow AMD partners in discussing future opportunities and collaborations.
We are proud to share that our CEO and Founder, Dr. Jonathan Graf, has been awarded the 2025 Brian Cohen Memorial Award at the IEEE International Symposium on Hardware Oriented Security and Trust (HOST). This honor recognizes Dr. Graf’s exceptional contributions to the field of hardware security, including his leadership in advancing secure hardware design, fostering industry-academic collaboration, and driving impactful innovation at Graf Research.
In his acceptance, Dr. Graf expressed gratitude to the mentors, colleagues, and collaborators who have shaped his journey, and reflected on the enduring legacy of Brian Cohen, whose passion for mentorship and advancing secure hardware continues to inspire the field.
This recognition underscores Graf Research’s commitment to advancing the state of hardware security and trust while honoring the values of leadership, service, and innovation that drive our work.
Graf Research is proud to announce our return to the 2025 SEE/MAPLD Conference, taking place May 12-16, 2025, in San Diego, California. As in years past, SEE/MAPLD brings together experts in the fields of radiation effects, microelectronics, FPGA design, and embedded systems.
At this year's conference, Graf Research will demonstrate Enverite PV-Bit verification and our Benches platform. Enverite PV-Bit verification ensures that the design contained in the FPGA bitstream is logically and physically equivalent to the netlist design. Enverite PV-Bit enhances the safety, security, and design integrity in mission-critical FPGA systems. Benches is our laboratory management platform that is designed for conducting complex experiments with a variety of lab equipment. Benches provides a flexible framework for testing the reliability of heterogeneous SoC-based systems under fault conditions.
We welcome all attendees to visit our booth to learn how Graf Research is advancing the security and assurance of programmable systems in the most demanding environments. For full conference details and registration, visit the SEE/MAPLD 2025 website.
Graf Research is excited to exhibit the Enverite EDA Suite at HOST 2025! Enverite PV-Bit verification advances hardware security, functional safety, and FPGA design assurance through bitstream verification. Come talk to us about how Enverite PV-Bit can help you on May 6th and 7th!
We’ll also be sharing opportunities through the Graf Research Intern Program! Students who are passionate about FPGA assurance and EDA innovation can gain valuable experience working at Graf Research.
Come see Enverite PV-Bit by Graf Research in action at the FCCM Demo Night on May 5th, 2025! Enverite PV-Bit is our innovative solution for bitstream verification, helping improve FPGA design assurance and ensuring the integrity and security of programmable hardware systems.
Interested in joining us? We’re also highlighting opportunities through the Graf Research Intern Program — a unique chance for students to work hands-on with FPGA security, EDA tooling, and hardware verification challenges.
If you’re attending FCCM, don’t miss the chance to chat with our team about how Enverite PV-Bit verification can help you assure your FPGA design.
Graf Research will be demonstrating the Enverite EDA suite at GOMACTech 2025. Stop by booth 304 in Pasadena, California, from March 18-19, to see a demonstration of Enverite PV-Bit performing FPGA bitstream verification. For more information about GOMACTech 2025, visit their website here.
We’re also presenting three papers at GOMACTech 2025. Our papers discuss the use of the EnsofIC Attest platform for non-destructive evaluation of counterfeit FPGAs (P.110), the use of Benches laboratory management software for system-level fault injection (P.60), and how Enverite PV-Bit verification can be paired with Siemens Questa Equivalent FPGA to improve FPGA safety and security policy compliance.
GOMACTech 2025 Multidisciplinary Approaches to Security
March 20, 2025, 8:20-10:00 AM
FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking
Jonathan Graf, Margaret Winslow, Evan Drinkert, Kevin Urish, and John Hallman
Abstract: Security and safety policies across domains such as embedded security, defense safety, and automotive safety have been updated to require the ability to prove the design in an FPGA bitstream matches the anticipated function and structure specified in a designer’s source. Until recently, there were no commercial tools to meet these requirements. Now, emerging tools for bitstream equivalence checking can be paired with established tools for logic equivalence checking to create a verification chain that satisfies these new policy demands. This paper explores three example safety and security policies that call for such verification. A demonstration design is evaluated with logic and bitstream equivalence checking tools, and the output files are enumerated to seamlessly link the conclusions of each tool to policy requirements. Finally, additional assurance requirements that can be met by pairing bitstream equivalence checking tools with other verification techniques are explored.
GOMACTech 2025 Poster Session
March 20, 2025, 10:30-12:00 PM
Towards Synthetic Data Generation for Characterization of FPGAs
Whitney Batchelor, Cody Crofford, Margaret Winslow, Mia Taylor, Kevin Paar, James Koiner, Scott Harper
Abstract: Both the increasing use of machine learning to reason over features relevant to microelectronics and the ongoing threats to the microelectronics supply chain necessitate the need to explore novel methods for characterizing and identifying known good microelectronic devices. Unfortunately, obtaining a statistically relevant number of devices for evaluation is infeasible due to cost and supply chain issues. This leads to a constant deficit in data obtained from good devices that could be used for machine learning reasoning or known good device characterization. Synthetic data generation for use in machine learning training is growing in popularity but comes with its own set of challenges. Here, we present a method for synthetically generating field programmable gate array data that can not only be used to train models for our FPGA counterfeit device detection solution but generally used as characterization data for known good FPGAs.
System-Level Fault Injection on Heterogeneous System-on-Chips
Edward Carlisle IV, James Koiner, Evan Ezell, Scott Harper
Abstract: This paper presents a system-level approach to fault injection on heterogeneous System-on-Chip devices. Our approach simultaneously targets multiple resource types while taking care to maintain transparency of the fault injector and minimize constraints on the end user design. The approach integrates with the Benches laboratory management platform to enable fully automated operation and provide campaign analysis features. The platform can also be leveraged to automate radiation testing.
Graf Research is excited to announce that we are exhibiting our Enverite PV-Bit verification tool at the International Symposium on Field-Programmable Gate Arrays (ISFPGA) 2025. FPGAs power some of the most vital systems across industries, including defense, aerospace, automotive, and telecommunications. Ensuring the integrity of FPGA bitstreams is crucial to preventing unauthorized modifications or implementation errors within an FPGA design. Enverite PV-Bit verification ensures the equivalence between the FPGA netlist and its corresponding bitstream to enhance FPGA design assurance.
ISFPGA takes place from February 27th through March 1st, 2025, in Monterey, CA. Come see our team at the exhibition to learn more about how Enverite PV-Bit verification impacts the hardware safety and security community. For more information on ISFPGA 2025, please visit their website.
Graf Research CEO, Dr. Jonathan Graf, is presenting alongside Kevin Urish from Siemens on the topic “Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream.” They cover how Enverite PV-Bit verification takes safety and security compliance evidence provided by Siemens EDA software and proves those claims hold in the final bitstream implementation. The webinar is presented live on Wednesday, February 19th! Register for the webinar at this link.
Dr. Ed Carlisle IV will present a poster titled "Improving Workforce Development with Laboratory Automation" at PAINE 2024. The session will take place on November 12, from 4:50 pm to 5:50 pm. Attendees can explore innovative approaches to enhancing workforce training through automation. For more information and registration, visit PAINE 2024
Improving Workforce Development with Laboratory Automation
Edward Carlisle IV, Scott Harper, Jonathan Graf
Abstract: Workforce development efforts that include laboratory components face many challenges, including budget constraints and limited access to equipment. We define the desired capabilities of a laboratory automation platform that can help overcome these challenges and expand the reach of workforce development efforts, accelerating the growth of a well-qualified workforce. This paper presents an automated microelectronics lab experimentation platform called Benches. We describe how Benches incorporates many of these desired features and provides additional benefits for workforce development efforts.
Dr. Ali Asgar Sohanghpurwala will present Graf Research's Enverite EDA Suite at the Altera FPGA Security User Working Group in the D.C. area this month. The presentation will highlight the advanced capabilities of Enverite tools in assuring the security and integrity of FPGA designs. Attendees will gain valuable insights into key security features of Altera FPGAs.
Graf Research is attending all three AMD Security Working Group 2024 events. We will have a booth at each Partner Showcase where attendees can discuss how the Enverite EDA suite addresses their specific FPGA security needs. Don't forget to register for the AMD Security Working Groups and attend the Partner Showcase events:
Longmont, CO, on Tuesday, October 15, 2024, from 6:00-9:00pm
Washington, DC, on Wednesday, November 13, 2024, from 5:30-8:30pm
Munich, Germany, on Tuesday, December 10, 2024, from 5:30-8:30pm
Image Credit: osmosis 2024 | Siemens Software
On October 17th, Graf Research is presenting at the Siemens osmosis 2024 event in Munich, Germany. Dr. Jonathan Graf will share insights into how the Enverite PV-Bit verification process drives design assurance into the deployed bitstream during his talk titled "Enverite PV-Bit: Bitstream Verification for FPGA Design Assurance." This event focuses on how EDA techniques overcome verification challenges and offers a platform for connecting with experts in the field. Registration for the conference is still open, and attendees can secure their spot through Siemens EDA Events.