News and Events
Graf Research’s James Koiner will be presenting his poster “Composing HTH Benchmarks for Evaluating Bitstream-level Detection Methods” at IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) on October 27th from 4:30-5:30pm in Phoenix, Arizona.
James Koiner will be presenting his poster “Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods” at ITC (International Test Conference) on October 14th from 12:00 – 2:00 PM in San Antonio, Texas. We are excited to learn more about advances in the electronic test of devices and Silicon Lifecycle Management. Interested in our research or Enverité software capabilities? Please reach out at grafresearch.com/contact-shift or email us at info@enverite.com!
Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
Freya Archuleta, James Koiner, Ali Asgar Sohanghpurwala, Whitney Batchelor, Jonathan Graf, Scott Harper
Hardware Trojan Horse (HTH) detection methods require benchmark sets that provide both sufficient scale and diversity to support meaningful evaluation. This work presents an ontology-guided HTH benchmark that programmatically composes Trojan-free golden designs with parameterized triggers and payloads to generate large populations of exploited designs. The benchmark captures design and HTH ontology metadata to support broad coverage and is extended with a workflow for generating bitstreams that approximate bitstream-level HTH insertion. As a case study, Bitstream Equivalence Checking (BEC) is evaluated using 26 golden designs and 7,089 attempted HTH insertions.
Our team is presenting “Enverité Forge-DV: Design & Verification EDA for AMD Adaptive SoCs” at every SWG event this year, including in Longmont, CO; Washington, D.C; and Munich, Germany.
Experience Forge-DV firsthand:
Explore real-world Forge-DV use cases,
See integration with existing design and verification workflows, and
Discover consistent, highly auditable security implementation across the FPGA lifecycle.
Learn more about AMD’s Security Working Group events and register here.
The Graf Research team is heading to Longmont, Washington, D.C., and Munich for the 2026 AMD Security Working Group series. Don’t miss out on the partner night events, where we’ll be discussing Enverité, our assurance EDA for the world’s most critical systems.
Longmont, CO – October 6-7
Washington, DC – November 3-4
Munich, Germany – December 8-9
We’re looking forward to connecting with the security community, discussing the latest design security challenges and solutions, and talking about how assurance can be built throughout the development lifecycle.
Learn more about the event and register through AMD.
Graf Research at Virginia Tech Engineering Expo 2026
On Tuesday, September 15th Graf Research will be recruiting at Virginia Tech’s 47th annual Engineering Expo!
We are excited to announce that the 1.2026.2 release of our Enverité PV-Bit software is now available!
The 1.2026.2 release includes support for the full AMD Zynq UltraScale+ RFSoC family and additional design security features. See full device support here: PV-Bit Support .
PV-Bit is the only Bitstream Equivalence Checker in the world! It verifies your FPGA configuration by proving the equivalence between the routed physical netlist and the configuration bitstream.
Stay tuned for Altera, Lattice, and Microchip device support!
If you or your team is interested in PV-Bit or any of our Enverité software features, please reach out here or email us at info@enverite.com.
Graf Research is proud to sponsor and exhibit at the 45th Digital Avionics Systems Conference (DASC), taking place September 13–17, 2026, in Orlando, Florida. This year’s conference focuses on Safe and Secure Digital Avionics in the Age of AI, making it a great opportunity to discuss our research and Enverité capabilities for safety and assurance in FPGA-based avionics systems. Stop by the Graf Research booth to meet the team and learn more.
We are also excited to announce that our paper, “Accelerating FPGA-Based Avionics System Recertification with Delta Verification Methodologies and Bitstream-Level Verification of Physical Isolation,” received a Best of Session Award. Dr. Ali Asgar Sohanghpurwala will present the paper on Tuesday, September 15th from 2:00–2:30 PM during the Tools for Data Management and Development session. The presentation will highlight our work applying delta verification and bitstream-level verification to FPGA-based avionics systems.
Learn more about DASC 2026 and view the conference program on the DASC website.
Accelerating FPGA-Based Avionics System Recertification with Delta Verification Methodologies and Bitstream-Level Verification of Physical Isolation
Ali Asgar Sohanghpurwala, Jonathan Graf, Evan Drinkert, Scott Harper, Meg Winslow
Field programmable gate arrays (FPGAs) offer a unique balance of performance, efficiency, and flexibility that make them uniquely suited for use in digital avionics. Avionics systems often support safety and security critical functions alongside non-critical functions. Ensuring the critical functions are implemented with sufficient fault tolerance is emphasized by standards bodies with stringent certification regimes. FPGA vendors aid in compliance by providing isolation design flows that enable containment of faults to specific hardware functions. Here we present how PV-Bit further assures such designs by verifying that isolation properties verified at the netlist-level are preserved in the bitstream via Bitstream Equivalence Checking (BEC). Furthermore, we present how this can be combined with the delta verification concept to narrow the recertification scope for certain FPGA design changes.
We're excited to share that Scott Harper, PhD, will participate in the DAC 2026 panel “From RTL to Reality: Building Security into the Silicon Lifecycle” on Monday, July 27, from 2:00 to 2:45 PM PDT at the DAC Pavilion.
The panel will examine how security can be established and maintained throughout the silicon lifecycle, from architecture and RTL design through verification, implementation, manufacturing, deployment, and post-deployment assurance.
Scott will contribute Graf Research’s perspective on verification and assurance for FPGA-based systems, an area closely related to the work behind our Enverité EDA tool.
If you're attending DAC, we hope you'll join the discussion and connect with Scott during the conference.
The Siemens Verification Academy is hosting a webinar on "Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream," covering verification workflows for FPGA designs from high-level languages through the final bitstream. Enverité PV-Bit bitstream equivalence checking is an integral piece of this verification workflow.
Whether you're working on safety, security, hardware assurance, or FPGA verification, this webinar offers a great opportunity to learn more about modern equivalence checking methodologies and FPGA verification flows. Register at Siemens Verification Academy.
Interested in learning how Enverité PV-Bit bitstream equivalence checking integrates with this verification flow? Reach out to start a conversation.
Graf Research attended the AMD Partner Summit in San Jose this week. The event provided excellent engagement with fellow AMD partners. Lizzie Burgiss and Dr. Ali Asgar Sohanghpurwala were able to learn, network, and collaborate with industry leaders. We are looking forward to future AMD partner events where we can share insights and explore product synergies.
For more information about our Enverité software capabilities, click here
We are excited to announce that the 1.2026.1 release of our Enverité PV-Bit software is now available!
PV-Bit is the only Bitstream Equivalence Checker in the world! It verifies your FPGA configuration by proving the equivalence between the routed physical netlist and the configuration bitstream.
The 1.2026.1 release includes support for the AMD Artix 7, UltraScale, UltraScale+, and Versal device families! See full device support at www.grafresearch.com/pvbit-support.
Stay tuned for Altera, Lattice, and Microchip device support!
Interested in PV-Bit or any of our Enverité software features? Please reach out at www.grafresearch.com/contact-shift or email us at info@enverite.com.
Graf Research is sponsoring IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) 2026, May 13th-16th.
Don’t miss Dr. Jonathan Graf’s talk about CAD for Configurable Computing Machine Security at the Workshop on Security for Custom Computing Machines (SCCM) on May 13th!
Stop by our booth to chat about our Enverité EDA software for FPGA assurance and verification, and to meet the famous Enveriteddy!
For more information about the event, click here.
Dr. Ed Carlisle will be attending the Single Event Effects (SEE) Symposium featuring the Systems-on-a-Chip (SoCs) for Space Workshop, May 11th-15th. The growth of this event shows the importance of FPGAs and SoCs in the Space Industry. For more information about the event, click here.
Interested in our research or Enverité software capabilities? Please reach out at info@enverite.com.
Graf Research is sponsoring IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2026 from May 4th-7th.
Whitney Batchelor will be on Panel 2: AI for Automating Hardware Security: Contribution or Fake News?
We will also have a booth showcasing our Enverité EDA software for FPGA assurance and verification, where Dr. Jonathan Graf and Lizzie Burgiss would love to chat with you about all things security and trust!
Interested in our research efforts or Enverité software? Please reach out at grafresearch.com/contact-shift or email us at info@enverite.com.
Graf Research will be participating in the 2026 DoD Anti-Tamper Conference from April 21–23 in Laurel, Maryland.
We’re looking forward to the NDIA T&AC meeting this Thursday, April 9, 2026, where Dr. Jonathan Graf will be presenting “Independent Sources of Truth for Evidence-Based Microelectronics Assurance.”
This talk explores how microelectronics assurance depends on creating, preserving, and evaluating independent sources of truth. Dr. Graf will highlight real-world applications of securing FPGA designs using evidence generated by Enverité FPGA assurance software.
Graf Research is heading to New Orleans for GOMACTech 2026. Stop by booth 433 from March 10-11 to see a demonstration of Enverite EDA. For more information about GOMACTech 2026, visit their website here. We’re also presenting two papers at GOMACTech 2026:
Session 48: Artificial Intelligence for Cyber-Secure Microelectronics (Paper No. 48.5)
March 12, 2026, 3:30 – 5:10 PM
Accelerating Netlist Reverse Engineering with Artificial Intelligence
Whitney Batchelor, Margaret Winslow, Cody Crofford, Carlton Fraley, Kevin Paar, Scott J. Harper
Poster Session: Trusted, Assured, and Cyber-Secure Microelectronics Posters (Poster No. P.96)
March 12, 2026, 10:30-12:00 PM
Bitstream-level Verification of Physical Isolation with PV-Bit
Ali Asgar Sohanghpurwala, Scott Harper, Jonathan Graf, Margaret Winslow, Whitney Batchelor, Tim Dunham
📅 International Symposium on FPGAs (ISFPGA) 2026
We are a silver sponsor and exhibitor at ISFPGA in Monterey, California, from February 23–24! For more information about ISFPGA, click here.
Stop by our booth and talk to Dr. Ali Asgar Sohanghpurwala and T.J. Given about how our Enverité EDA software supports FPGA assurance and verification in both safety- and security-critical applications.
Interested in an Enverité capability or need more information? Reach out here.
We are presenting at FPGA-forum 2026 in Trondheim, Norway, taking place from February 11th–12th. FPGA-forum brings together FPGA designers, researchers, and industry practitioners to exchange practical experience and discuss emerging topics within the FPGA community.
For more information about the event, visit the FPGA-forum website: FPGA Forum
Dr. Jonathan Graf, CEO of Graf Research, will be presenting a technical paper on Enverité PV-Bit entitled “Applications of Bitstream Equivalence Checking to High-Assurance FPGA-Based Systems.” The presentation will take place on Wednesday at 14:00, as part of the conference technical program.
We’ll be showcasing our Enverité software on the exhibitors’ floor both days. We welcome attendees to stop by and discuss how Enverité can support the verification of their FPGA-based systems. We look forward to connecting with the FPGA-forum community in Trondheim!
More information about Enverité can be found here.
We’re kicking off the new year with several updates to our Enverité features. Below are highlights from Forge, PV-Bit, and Trace as we head into 2026!
To rapidly test-drive Enverité software, contact info@enverite.com for an online or local demo of the Forge, PV-Bit, or Trace.
A demo version of the Forge Security Lifecycle Manager is now available. Forge is designed to simplify the management and proper configuration of security settings.
Want to see Forge in action or explore how it can strengthen your security workflow? Reach out to us at info@enverite.com to get set up with an interactive demo. Read more
PV-Bit continues to advance FPGA bitstream assurance for safety- and security-critical applications. Our upcoming 1.2026.1 release expands coverage to select AMD Versal devices, additional AMD UltraScale+ devices, and the full family of AMD Artix 7 devices.
For a detailed look at current device support in Enverité PV-Bit 1.2025.1, view the full compatibility list here.
Ready to explore what PV-Bit can do for your designs? Reach out to us anytime at info@enverite.com. Read more
For a limited time, you’ll receive Trace archiver at no extra charge with your Enverité PV-Bit purchase. Trace enhances PV-Bit by creating an auditable, reproducible digital thread of your FPGA design workflow.
We’ll be demonstrating Enverité at several upcoming events in Q1 and would love to connect with you in person. Catch us at FPGA Forum in Trondheim, Norway; ISFPGA in Monterey Bay, CA; and GOMAC in New Orleans, LA.
