IEEE HOST Symposium 2026

Graf Research is sponsoring IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2026 from May 4th-7th. 

Whitney Batchelor will be on Panel 2: AI for Automating Hardware Security: Contribution or Fake News?

We will also have a booth showcasing our Enverité EDA software for FPGA assurance and verification, where Dr. Jonathan Graf and Lizzie Burgiss would love to chat with you about all things security and trust!

Interested in our research efforts or Enverité software? Please reach out at grafresearch.com/contact-shift or email us at info@enverite.com.

NDIA Trust & Assurance Committee Invited Talk

We’re looking forward to the NDIA T&AC meeting this Thursday, April 9, 2026, where Dr. Jonathan Graf will be presenting “Independent Sources of Truth for Evidence-Based Microelectronics Assurance.”

This talk explores how microelectronics assurance depends on creating, preserving, and evaluating independent sources of truth. Dr. Graf will highlight real-world applications of securing FPGA designs using evidence generated by Enverité FPGA assurance software.

Enverite by Graf Research at GOMACTech 2026 in New Orleans!

Graf Research is heading to New Orleans for GOMACTech 2026. Stop by booth 433 from March 10-11 to see a demonstration of Enverite EDA. For more information about GOMACTech 2026, visit their website here. We’re also presenting two papers at GOMACTech 2026:

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Session 48: Artificial Intelligence for Cyber-Secure Microelectronics (Paper No. 48.5)

March 12, 2026, 3:30 – 5:10 PM

Accelerating Netlist Reverse Engineering with Artificial Intelligence

Whitney Batchelor, Margaret Winslow, Cody Crofford, Carlton Fraley, Kevin Paar, Scott J. Harper

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Poster Session: Trusted, Assured, and Cyber-Secure Microelectronics Posters (Poster No. P.96)

March 12, 2026, 10:30-12:00 PM

Bitstream-level Verification of Physical Isolation with PV-Bit

Ali Asgar Sohanghpurwala, Scott Harper, Jonathan Graf, Margaret Winslow, Whitney Batchelor, Tim Dunham

Enverité at ISFPGA 2026

📅 International Symposium on FPGAs (ISFPGA) 2026

We are a silver sponsor and exhibitor at ISFPGA in Monterey, California, from February 23–24! For more information about ISFPGA, click here.

Stop by our booth and talk to Dr. Ali Asgar Sohanghpurwala and T.J. Given about how our Enverité EDA software supports FPGA assurance and verification in both safety- and security-critical applications.

Interested in an Enverité capability or need more information? Reach out here.

Enverité at FPGA Forum 2026

We are presenting at FPGA-forum 2026 in Trondheim, Norway, taking place from February 11th–12th. FPGA-forum brings together FPGA designers, researchers, and industry practitioners to exchange practical experience and discuss emerging topics within the FPGA community. 

For more information about the event, visit the FPGA-forum website: FPGA Forum 

Dr. Jonathan Graf, CEO of Graf Research, will be presenting a technical paper on Enverité PV-Bit entitled “Applications of Bitstream Equivalence Checking to High-Assurance FPGA-Based Systems.” The presentation will take place on Wednesday at 14:00, as part of the conference technical program. 

We’ll be showcasing our Enverité software on the exhibitors’ floor both days. We welcome attendees to stop by and discuss how Enverité can support the verification of their FPGA-based systems. We look forward to connecting with the FPGA-forum community in Trondheim!

More information about Enverité can be found here.

January Enverité Updates

January Enverité Updates

We’re kicking off the new year with several updates to our Enverité features. Below are highlights from Forge, PV-Bit, and Trace as we head into 2026!

Demo Enverité Software

Online and Local Versions Available

To rapidly test-drive Enverité software, contact info@enverite.com for an online or local demo of the Forge, PV-Bit, or Trace.

Enverité Forge

A demo version of the Forge Security Lifecycle Manager is now available. Forge is designed to simplify the management and proper configuration of security settings.

Want to see Forge in action or explore how it can strengthen your security workflow? Reach out to us at info@enverite.com to get set up with an interactive demo. Read more

Enverité PV-Bit

PV-Bit continues to advance FPGA bitstream assurance for safety and security critical applications. Our upcoming 1.2026.1 release expands coverage to select AMD Versal devices, additional AMD UltraScale+ devices, and the full family of AMD Artix 7 devices.

For a detailed look at current device support in Enverité PV-Bit 1.2025.1, view the full compatibility list here.

Ready to explore what PV-Bit can do for your designs? Reach out to us anytime at info@enverite.com. Read more

Enverité Trace

For a limited time, you’ll receive Trace archiver at no extra charge with your Enverité PV-Bit purchase. Trace enhances PV-Bit by creating an auditable, reproducible digital thread of your FPGA design workflow.

Read more

Upcoming Events

We’ll be demonstrating Enverité at several upcoming events in Q1 and would love to connect with you in person. Catch us at FPGA Forum in Trondheim, Norway; ISFPGA in Monterey Bay, CA; and GOMAC in New Orleans, LA. 

Pint it Forward this Veteran’s Day Weekend at Moon Hollow Brewing

Starting Friday, November 7th, we invite veterans and their loved ones to stop by Moon Hollow Brewing to enjoy a drink on us. Thank you, veterans.

Graf Research at IEEE SecDev 2025: Advancing FPGA Design Verification with Enverite PV-Bit

Graf Research is proud to announce that Dr. Ali Asgar Sohanghpurwala will present at IEEE SecDev 2025 on “PV-Bit: Private Verification of FPGA Bitstreams Via Bitstream Equivalence Checking.”

This talk will explore the theory and practice of private verification, showing how PV-Bit enables organizations to confirm bitstream equivalence without exposing sensitive design details. Dr. Sohanghpurwala will detail how we evaluated PV-Bit against an open-source design set for both false positives in unmodified designs and accurate detection for designs with fault injections.

PV-Bit represents a key advance in protecting both intellectual property and mission-critical systems. We look forward to sharing our latest research with the SecDev community and advancing the state of practice in secure hardware design.

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PV-Bit: Private Verification of FPGA Bitstreams Via Bitstream Equivalence Checking
Ali Asgar Sohanghpurwala, Daniel Gibson, Scott Harper, Jonathan Graf, Timothy Dunham

Established FPGA design verification flows utilize sophisticated methods to provide assurance for microelectronic designs deployed on FPGA based systems, but they lack visibility into the vendor proprietary configuration bitstream format.  This means the assurances they provide only extend as far as the post place and route simulation netlist, leaving a verification gap where errors or malicious modifications could be introduced during the bitstream generation process.  Here, we discuss and evaluate the operation and efficacy of PV-Bit as a tool that can address this gap via Bitstream Equivalence Checking: proving physical (and thus functional) equivalence between the bitstream and a verified, trusted netlist.  PV-Bit uniquely performs this check without exposing private Intellectual Property included in the bitstream.

Graf Research at the AMD Security Working Group

At the upcoming AMD Security Working Group, Graf Research will share our latest contributions to advancing FPGA security and assurance.

Our joint presentation with AMD, “Isolation Design Flow / Verifying Isolation at the Bitstream Level”, will demonstrate how engineers can design with confidence by validating critical isolation properties in the FPGA bitstream. We will also introduce the Forge Security Lifecycle Manager, a new tool that streamlines assurance throughout the hardware development process.

Beyond our technical sessions, we are excited to connect with partners and colleagues during Partner Night, where we’ll discuss the broader Enverite suite and its role in strengthening the FPGA security ecosystem. Don’t miss this opportunity to engaging in meaningful collaboration with the wider security and semiconductor community.

• Longmont, CO, from October 14 – 15, 2025

• Washington, D.C., from November 5 – 6, 2025

• Munich, Germany, from December 9 – 10, 2025

For more information, visit https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/design-security.html#security-working-group

Graf Research Presents on Mathematical Approaches to Microelectronics Assurance at PAINE 2025

Graf Research is proud to share that our Director of Research, Whitney Batchelor, is presenting at PAINE 2025. Her talk, “Mathematical Approaches to Microelectronics Assurance,” will highlight how mathematics is not just a supporting tool but a core element in addressing assurance challenges in microelectronics. Whitney will demonstrate how a deeper mathematical perspective enables stronger, more reliable methods for ensuring trust in microelectronic systems. We look forward to Whitney’s vision setting the stage for important conversations at PAINE 2025.

Graf Research at DASC 2025

Graf Research is excited to attend DASC 2025, where we will discuss the impact of Enverite PV-Bit on avionics safety. Be sure to visit our booth to learn more about how Enverite by Graf Research is helping shape the future of safety and security in FPGA-based avionics systems.

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Accelerating Recertification of FPGA-Based Avionics Systems via Bitstream Equivalence Checking

Jonathan Graf, Evan Drinkert, Scott Harper, Margaret Winslow, Alan Cook, Ali Asgar Sohanghpurwala, Tim Dunham, and Wilfredo Tabada

Field programmable gate arrays (FPGAs) are ubiquitous in avionics.  While FPGAs are easily reprogrammable, update cycles can be long even for minor changes due to recertification testing requirements.  Formal verification software can provide proofs about some portions of the FPGA re-design process, but standard formal verification software cannot validate the final FPGA bitstream design.  A new software technique, Bitstream Equivalence Checking (BEC), can prove the logical and physical equivalence of an FPGA bitstream to a physical netlist representation.  Used in concert with Logic Equivalence Checking (LEC) as well as timing and physical design analysis tools, BEC enables a new delta verification flow that defines the relationship between an original, certified FPGA bitstream and the bitstream that results after minor updates to the source code.  This paper explains the process and illustrates its application to an example AMD Xilinx FPGA design when modified with a variety of source changes.  The consequences of applying the process to avionics systems recertification are explored.

Graf Research at FPL 2025

Next week, Graf Research is heading to FPL 2025 with two talks and a demo showcasing our latest work in FPGA security. Dr. Jonathan Graf will be talking about “Securing Custom Computing Devices: Observations from the Lab and Market” at the SCCM workshop. Whitney Batchelor is presenting how Graf Research R&D efforts led to the development of our Enverite EDA suite. Lastly, at demo night, Dr. Graf will demonstrate how Enverite PV-Bit bitstream equivalence checking detects a Hardware Trojan directly inserted into a bitstream.

Learn more about the event: https://2025.fpl.org/

Enverite PV-Bit Demonstration at FPGA Conference Europe 2025

Join us as Dr. Jonathan Graf, CEO of Graf Research, presents a technical talk and demonstration of Enverite PV-Bit. Enverite PV-Bit extends equivalence checking into the bitstream, allowing users to verify that the deployed bitstream accurately represents the original design. 

We’ll also be hosting a booth at the conference. Come speak directly with our engineers and discover how Enverite PV-Bit can streamline your verification process and improve the safety and security of your FPGA deployments. We’re looking forward to connecting with the FPGA community in Munich!

 For more information about the conference, visit FPGA Conference Europe.

Graf Research at DAC 2025

Graf Research will be at DAC in San Francisco, California, from June 23 - June 25. DAC is the premier event for design and automation in electronics. We’re excited to engage with engineers, researchers, and innovators shaping the future of microelectronic systems.

Visit us at booth 2128, where our engineering team will be providing demonstrations of the Enverite PV-Bit product. Bitstream equivalence checking with Enverite PV-Bit can augment your FPGA toolchain to increase the safety, security, and assurance of your system.

Learn more about DAC, the Design Automation Conference.

Graf Research at the AMD Premier Partner Summit 2025

Graf Research is attending the AMD Premier Partner Summit 2025 in San Jose from June 17-19. This summit is always a great opportunity for learning, networking, and building meaningful technical partnerships. We are especially excited to highlight Enverite PV-Bit, our bitstream equivalence checking tool, and its applicability in safety- and security-critical fields. We look forward to joining fellow AMD partners in discussing future opportunities and collaborations.

Graf Research CEO Dr. Jonathan Graf Receives the 2025 Brian Cohen Memorial Award at IEEE HOST

We are proud to share that our CEO and Founder, Dr. Jonathan Graf, has been awarded the 2025 Brian Cohen Memorial Award at the IEEE International Symposium on Hardware Oriented Security and Trust (HOST). This honor recognizes Dr. Graf’s exceptional contributions to the field of hardware security, including his leadership in advancing secure hardware design, fostering industry-academic collaboration, and driving impactful innovation at Graf Research.

In his acceptance, Dr. Graf expressed gratitude to the mentors, colleagues, and collaborators who have shaped his journey, and reflected on the enduring legacy of Brian Cohen, whose passion for mentorship and advancing secure hardware continues to inspire the field.

This recognition underscores Graf Research’s commitment to advancing the state of hardware security and trust while honoring the values of leadership, service, and innovation that drive our work.

Graf Research Exhibiting Enverite EDA Suite and Benches Platform at SEE/MAPLD 2025

Graf Research is proud to announce our return to the 2025 SEE/MAPLD Conference, taking place May 12-16, 2025, in San Diego, California. As in years past, SEE/MAPLD brings together experts in the fields of radiation effects, microelectronics, FPGA design, and embedded systems.

At this year's conference, Graf Research will demonstrate Enverite PV-Bit verification and our Benches platform. Enverite PV-Bit verification ensures that the design contained in the FPGA bitstream is logically and physically equivalent to the netlist design. Enverite PV-Bit enhances the safety, security, and design integrity in mission-critical FPGA systems.  Benches is our laboratory management platform that is designed for conducting complex experiments with a variety of lab equipment. Benches provides a flexible framework for testing the reliability of heterogeneous SoC-based systems under fault conditions.

We welcome all attendees to visit our booth to learn how Graf Research is advancing the security and assurance of programmable systems in the most demanding environments. For full conference details and registration, visit the SEE/MAPLD 2025 website.

Enverite Exhibit at HOST 2025!

Graf Research is excited to exhibit the Enverite EDA Suite at HOST 2025! Enverite PV-Bit verification advances hardware security, functional safety, and FPGA design assurance through bitstream verification. Come talk to us about how Enverite PV-Bit can help you on May 6th and 7th!

We’ll also be sharing opportunities through the Graf Research Intern Program! Students who are passionate about FPGA assurance and EDA innovation can gain valuable experience working at Graf Research.

Enverite PV-Bit at FCCM Demo Night!

Come see Enverite PV-Bit by Graf Research in action at the FCCM Demo Night on May 5th, 2025! Enverite PV-Bit is our innovative solution for bitstream verification, helping improve FPGA design assurance and ensuring the integrity and security of programmable hardware systems.

Interested in joining us? We’re also highlighting opportunities through the Graf Research Intern Program — a unique chance for students to work hands-on with FPGA security, EDA tooling, and hardware verification challenges.

If you’re attending FCCM, don’t miss the chance to chat with our team about how Enverite PV-Bit verification can help you assure your FPGA design.