Enverité® PV-Bit® Bitstream Equivalence Checker verifies the FPGA design is properly implemented in the bitstream by proving the physical equivalence between the physical netlist and the bitstream.

Traditional verification techniques stop at the netlist, exposing programs to increased risk and often requiring expanded testing before deployment. The PV-Bit feature is the only commercially available bitstream equivalence checker that can independently verify the bitstream format that is deployed on the FPGA.

Bitstream Equivalence Checking (BEC) compares configuration expectations between the trusted physical netlist and the bitstream in a property-based comparison domain. It proves both logical and physical equivalence, enabling verification results established at the netlist level to carry forward into the deployed configuration.

Design & Attestation Report

PV-Bit software generates cryptographically signed reports documenting the equivalence verification result between the physical netlist and bitstream. For each evaluated design, it generates a design report showing any matches and mismatches of design resources. It produces attestation reports enumerating all configuration properties checked by PV-Bit BEC. The design report, attestation report, and their associated signatures serve as assurance evidence of netlist-to-bitstream equivalence.

Safety Verification

Standards such as DO-254, ED-80, ISO 26262, IEC 61508, IEC 62566, and FPGA security specific guidance increasingly expect that verification evidence extends to the configuration bitstream. PV-Bit BEC provides verification between the formally verified HDL and the final bitstream.

Security Verification

Security-critical systems must detect unintended changes to the bitstream, whether accidental (e.g., implementation errors) or malicious (e.g., hardware Trojans). BEC provides an operational mechanism to verify the absence of unapproved changes in the bitstream without disclosing protected configuration formats.

Delta Verification

PV-Bit BEC verifies that a modified FPGA bitstream differs from the original only by the intended logical and physical changes by comparing both bitstreams at the configuration level. When engineering change orders are rigorously evaluated, BEC permits certification authorities to focus testing on the specific scope of the change, reducing unnecessary testing during recertification.

Functional Isolation Verification

In FPGA systems that depend on functional isolation for security or fail-safe behavior, certification can hinge on verifying the strict physical isolation of hardware modules in the deployed configuration. PV-Bit BEC verifies that isolation boundaries enforced during implementation remain intact in the deployed bitstream.