Design & Verification Manager for Adaptive SoC Security


Forge-DV™ Design and Verification Manager empowers developers to produce designs meeting the highest levels of security by enabling efficient implementation and verification of complex security features in Adaptive SoCs. Industry standards, program requirements, and configurable security features in platforms are continuously evolving to address a growing attack surface. Manually interpreting and applying this guidance across tool flows is complex and error-prone. Forge-DV transforms security guidance into structured decisions, assists with the proper configuration of complex security features, verifies security feature implementation, and generates reports that document realized security objectives in the final design.

Process Overview

Forge-DV enables users, from novice designers to advanced security engineers, to make, implement, and verify security decisions while supporting flexible integration with existing development workflows.

  • Make Informed Decisions: Forge-DV prompts users through security decisions with contextual information on security features, potential attack vectors, implementation considerations, and available mitigations and countermeasures.

  • Leverage HSIGs: Hardware Security Implementation Guides (HSIGs) derived from industry standards, vendor documentation, and program requirements, guide security feature configuration and implementation throughout the Forge-DV workflow.

  • Flexible Implementation Workflows: Forge-DV maps the selected security approaches to device-specific security features and translates decisions into actionable implementation steps. Implementation can be performed directly in the Forge-DV interface or in external development tools.

  • Verify Implementation: Forge-DV drives verification activities through verification connectors, which prove the selected security measures have been correctly implemented.

  • Capture Evidence and Report Out: Forge-DV captures security decisions, configurations, implementation artifacts, and verification results to produce auditable reports and artifacts that document the security engineering process and provide evidence that the final bitstream or Programmable Device Image (PDI) contains the appropriate and correctly implemented security measures to meet developer goals.

Hardware Security Implementation Guides (HSIGs)



Forge-DV formalizes security requirements through Hardware Security Implementation Guides (HSIGs), providing structured, actionable guidance for implementing security features. Device HSIGs capture available device security features and the decisions, configurations, implementation operations, and verification activities required to implement them. Policy HSIGs apply security requirements as constraints to Device HSIGs, tailoring the available implementation choices to the requirements of a specific policy or program.

Forge-DV Security Decisions


Selecting appropriate security options is critical for programs where a misinterpretation or incorrect security feature implementation can result in an exploitable weakness. Forge-DV guides users through decisions relevant to the selected HSIGs to support consistent implementation of security requirements. Once all necessary decisions have been made, Forge-DV provides actionable steps required to implement and verify the selected security features in the resulting design.

Forge-DV Auditable Evidence & Reporting Features


Forge-DV produces a signed report bundle containing project selections, implementation logs, design artifacts, and final verification results, along with a signed summary report containing hashes of the bundle contents. Together, these artifacts provide a traceable record of the security engineering process and attest to the correct implementation of the selected security measures in the final design format.

 

Forge-DV Interest Survey


Forge-DV is currently available for demonstration. Broader support and access will be available in 2027. If you are interested in how Forge-DV can help your Adaptive SoC design or verification flow, fill out the survey below.

 
 

This page contains forward-looking information about Graf Research technologies and is subject to change.