bitstream equivalence checking accelerates recertification of FPGA designs in highly regulated industries by providing evidence that the ECO change was the only alteration to the certified bitstream.
Delta Verification of an Engineering Change Order
Recertification of updates to FPGA-based systems in heavily regulated industries can be as expensive and time consuming as the original certification. Enverité® PV-Bit® Bitstream Equivalence Checking (BEC) enables a delta verification flow to accelerate the process by providing evidence that the changes between the original bitstream and the bitstream fixed by an Engineering Change Order (ECO) are well defined and minimal. Enverité PV-Bit BEC paired with a logic equivalence checking (LEC) tool can prove that the HDL-described ECO change was the only logical alteration to the certified bitstream. Paired with timing and power re-analysis on the physical netlist, this may reduce and focus recertification testing.
Delta Verification Process
A tool chain may be established to verify the relationship between the certified bitstream and the bitstream with the ECO change, exposing and formally defining the differences between them.
Bitstream to physical netlist equivalence check of the original design with Enverité PV-Bit BEC
Physical netlist to HDL source equivalence check of the original design with LEC software
Implementation of the ECO (Delta) at the HDL level
Synthesis of the Delta HDL source; logical equivalence check with the Delta physical netlist; timing and power analysis of the Delta physical netlist using original constraints
Bitstream synthesis of the Delta physical netlist and a physical and functional equivalence check with the Delta bitstream using Enverité PV-Bit verification
Once complete, the process proves the Delta is the only logical change between the original and updated bitstreams.