News and Events
Graf Research has been awarded a Phase 1 SBIR to research and develop optimal strategies for cloud-based trust assessment. We anticipate creating not only a novel cloud architecture that can facilitate the use of many of the DARPA-sponsored custom microelectronics trust software tools but also a unique, cloud-hosted software product OpTrust-C which will devise optimal strategies for the proper implementation of defensive measures.
Continuing our publication of the applications of Game Theory to various levels of trust assessment, we discuss system-level applications in our IEEE NAECON 2016 paper. Come on out and see our presentation!
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Towards System-Level Adversary Attack Surface Modeling for Microelectronics Trust
Jonathan Graf
Abstract: Models of trust for microelectronic systems are difficult to create due to the large variety of adversarial strategies available. Building on previous work, we present a new adversary model that considers the large heterogeneous attack surface that is realistically available on a diverse microelectronic system. We also present an expanded game theoretic model that permits reasoning about optimal adversarial and defensive strategies across this varied attack surface.
Graf Research has been awarded a Phase 1 SBIR entitled "Irrefutable Tamper Logging." On this project, we will create the GR-TLogger, a tamper logger that makes use of the key management capabilities of next-generation secure FPGAs to store tamper logs that are information rich, semi-permanent, and irrefutable.
Jonathan Graf will be presenting an invited lecture entitled "FPGA Trust: Threats, Methods, Metrics, and Optimization" to the Hardware Security Symposium at the Potomac Institute for Policy Studies on May 2, 2016.
Jonathan Graf of Graf Research along with co-presenter Dale Reese of Idaho Scientific will be giving an invited lecture to Virginia Tech's Center for Embedded Systems for Critical Applications (CESCA). The topic is "FPGA MPSoC Security: Design and Runtime." Come on out and hear us! Details below:
FPGA MPSoC Security: Design and Runtime
Jonathan Graf, Founder, Graf Research; Dale Reese, Founder and Chief Scientist, Idaho Scientific
2:30pm - 3:30pm on April 15, 2016 (Friday) at Whittemore Hall 457
Abstract: An emerging class of Field Programmable Gate Array (FPGA) – the Multi-Processor System on Chip (MPSoC) – holds enormous promise for novel processing architectures in a variety of domains. Within the context of high-security systems, the same-die close coupling of heterogeneous processing structures with hardened security resources is of particular interest. Modern FPGA MPSoCs provide not only programmable FPGA fabric, ARM CPUs, graphics processor units (GPUs), and digital signal processors (DSPs) but also cryptographic accelerators, physically unclonable functions (PUFs), and hardware random number generators (HRNGs). This pairing of processing and security resources raises the possibility of using them to create tightly integrated, custom secure processors for emerging networked applications that demand the highest security standards. FPGA MPSoCs hold the potential of revolutionizing the security posture for high-security Internet of Things (IoT) applications such as autonomous vehicles, intelligent energy grid devices, home and industrial automation, cyber-physical systems – and even the datacenter.
In this seminar, Jonathan Graf (Graf Research) and Dale Reese (Idaho Scientific) will introduce the variety of embedded computing security disciplines that meet within the confines of FPGA MPSoCs. Security must be built into these devices from the moment they are first designed, all the way through their supply chains, during the development of each piece of software and firmware, and throughout every runtime operation of each disparate processing structure. Collectively, this makes the FPGA MPSoC an exciting new device class with exceptional opportunities for new embedded computing security innovation.
We are continuing to publish our research on the use of Game Theory to optimize hardware Trojan detection processes in our paper at IEEE HOST 2016. Make sure to come by and chat with us!
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Trust Games: How Game Theory Can Guide the Development of Hardware Trojan Detection Methods
Jonathan Graf
Abstract: The development of circuit testing and verification methods is commonly driven by formal analysis centered on an abstract mathematical model of the error or defect the method is designed to detect. Hardware Trojans, however, confound attempts to develop simple representative models due to the varieties of their physical embodiments in a circuit and the creative nature of a rational human adversary. Since it is nonetheless desirable to have a mathematical framework for determining the effectiveness of hardware Trojan detection methods, we present a game theoretic framework for so doing. Modeling the Trojan maker and detection method designer as opposing players in a 2-person strategic game is a necessary step in our process. However, the ultimate utility of the approach depends on an accurate security economic model of both players that can correctly consider the players’ incentives, empirically-derived detection method efficacy metrics, a comprehensive taxonomy of hardware Trojans, and the places in the design cycle of the circuit where the Trojan insertion and detection occur. In this paper, we present such a security economic model and the resulting game, which we call the Trust Game. We illustrate the value of this game primarily in the context of how it may guide the development of new hardware Trojan detection methods. We solve a representative game, illustrating the value of two common solution concepts, the iterated elimination of dominated strategies and Nash equilibrium. We further show that this framework has utility to both of the opposing players in the game. Finally, we recommend the development of standardized Trust Games that can be used to quickly measure the efficacy of both new hardware Trojans and hardware Trojan detection methods.
We're going to GOMAC this year to present our paper, "Toward Optimal Hardware Trojan Detection through Security Economics and Game Theory." Come on out to see us!
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Toward Optimal Hardware Trojan Detection through Security Economics and Game Theory
Jonathan Graf
Abstract: We present a security economic model that informs the optimal selection of hardware Trojan detection strategies. Our model accurately represents the economics and efficacy of available verification and Trojan detection methods and accounts for the varieties of available hardware Trojans. Paired with game theoretic analysis, this model informs ASIC/FPGA designers and associated policy makers of optimal defensive strategies.
It’s a first for Graf Research! Jonathan Graf has been invited to give a talk at the Industrial Security Working Group Panel on FPGA Configuration Security. The topic is “Threats to FPGA Configuration Security: The (Alarming!) Sophistication of Academic Exploits.” This will be the first time that Graf Research Corporation is represented at a conference, and certainly not the last!
Jonathan Graf will be attending the Xilinx Security Working Group in Longmont, CO from October 26-28. Be sure to say hello and chat about our upcoming research!
Graf Research has been founded!
