Viewing entries tagged
fpga

XSWG 2017: "Irrefutable Tamper Logging through FPGA Key Management"

Graf Research will be presenting our work on “Irrefutable Tamper Logging through FPGA Key Management” at both US Xilinx Security Working Groups: Longmont, Colorado (Oct 17-19) and Herndon, Virginia (Nov 7-9).   Co-authors include Jonathan Graf and Ali Asgar Sohanghpurwala from Graf Research and Matthew French and Dr. Andrew Schmidt from USC-ISI.  Register for the conference and come see us!

SEE/MAPLD 2017 Invited Lecture: "Optimizing Forward Design Trust for FPGAs"

Jonathan Graf will present an invited lecture on "Optimizing Forward Design Trust for FPGAs" at the 2017 Single Event Effects Symposium / Military and Aerospace Programmable Logic Devices Workshop in San Diego on May 25.  Come on out and see us!

Optimizing Forward Design Trust for FPGAs

Jonathan Graf

Abstract: Graf Research Corporation is developing a workflow to enable optimal forward design trust for Field Programmable Gate Arrays.  This flow is enabled by a blend of commercial EDA software, Graf Research specialized tools and techniques, and, as needed, custom trust analysis tools and techniques.  Custom tools include PV-Bit, which bridges the current gap between a trusted gate level netlist and the FPGA bitstream, bringing trust all the way into the bitstream.  To develop a trusted gate-level netlist, other trust analysis techniques must have preceded the use of PV-Bit.  The Graf Research contribution during synthesis, map, place, and route steps, is a tool called OpTrust, which uses a game theoretic decision engine to prescribe the optimal set of tests for the trust analysis of a design based on current threat data, the criticality of the design, and the availability of commercial verification or custom hardware Trojan detection methods.  Another element of trusted design is trusting the 3rd-Party IP cores present in the design.  The end goal of this assessment flow is to put the trust analysis of FPGA designs within the reach of the FPGA developer.  That is, we wish to ensure that the developer might perform the trust analysis themselves, pushing trust forward as each step in the design process is completed, concluding with a trusted bitstream.

Graf Research and USC-ISI Publish Research Results

Graf Research and the University of Southern California's Information Sciences Institute have published our work on “Irrefutable Tamper Logging through FPGA Key Management” at the 2017 DoD Anti-Tamper Conference.  Co-authors include Jonathan Graf and Ali Asgar Sohanghpurwala from Graf Research and Matthew French and Dr. Andrew Schmidt from USC-ISI.

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Graf Research Awarded BAA: DPA Title III Trusted FPGAs

Graf Research has been awarded a Phase 0 BAA research project entitled DPA Title III Trusted FPGAs.  

Brief Program Summary: The Department of Defense (DoD) and Intelligence Community (IC) have identified Field Programmable Gate Arrays (FPGAs) as a critical enabling technology across a wide variety of present and future systems. Advanced, commercially available FPGAs do not meet DoD's requirements for Trusted Systems as they are manufactured in un-Trusted fabrication facilities, primarily off-shore, and are considered vulnerable to tampering and insertion of malicious software and/or hardware. This program seeks to improve the security posture and reduce the risk associated with FPGA technology by addressing security concerns in the design, development, fabrication and supply lifecycle of FPGA devices. The purpose of this study is to conduct an analysis and develop an approach to ensure the availability of advanced “Trusted” and space qualified re-programmable FPGAs technology to support DoD/IC applications including satellite and strategic missile systems. “Trust” is defined as assurance of the integrity and availability of a product wherein that product will reliably operate as intentionally designed and not contain any malicious hardware and/or software that will compromise the intended application; e.g., exfiltration of sensitive data, etc. Efforts envisioned during this Phase 0 study include: analysis of current FPGA manufacturing capabilities; analysis of future technical capabilities needed to meet the needs of the FPGA market (USG and commercial); creation of a draft technical plan and schedule to establish a Trusted source for space qualified FPGA devices, to include (non-binding) high-level cost projections, to establish quantitative “Trust” criteria for FPGAs; identification and analysis of the markets for FPGAs; and identification of business strategies to ensure long term success in the Trusted and space qualified FPGA market.

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