We are excited to announce that Graf Research will be demonstrating Enverite PV-Bit verification in booth 719 at GOMACTech 2024. Make sure to stop by our booth to in Charleston, South Carolina, from March 19-20, 2024.
Enverite EDA offers a comprehensive suite of tools designed to address the critical challenges facing FPGA designers in ensuring the security, integrity, and assurance within their designs. Attendees at GOMACTech 2024 will have the opportunity to see a demonstration of Enverite PV-Bit verification. Engage with our experts at the booth and discuss PV-Bit verification of bitstream integrity, or other Enverite features. The Enverite EDA suite also offers the Trace archiver for tamper-evident digital thread creation and the Retrace auditor for automated auditing and reproduction of traced builds.
FPGA designers seeking to enhance their design assurance process can acquire Enverite EDA and unlock its full potential to streamline workflows, mitigate risks, and deliver mission-critical FPGA designs with unmatched assurance.
See Press Release for more information.
We’re also presenting two papers at GOMACTech 2024 in March – a poster and a presentation. Our papers discuss our EnsofIC Attest platform for non-destructive evaluation of counterfeit FPGAs and the role of EDA, including our Enverite EDA suite, in accelerating the development of high assurance FPGAs.
GOMACTech 2024 Nontraditional Approaches to Trust Session
March 19, 2024, 1:30-3:10 PM
Non-Destructive Evaluation of Repackaged Counterfeit FPGAs via Machine Learning
Whitney Batchelor, James Koiner, Cody Crofford, Kevin Paar, Margaret Winslow, Mia Taylor, Scott Harper
Abstract: With ongoing microelectronic supply chain issues, the demand for genuine field-programmable gate arrays (FPGAs) is increasing – but so is the occurrence of counterfeit devices. Frequently, devices are used, salvaged from old systems, and repackaged as new. These recycled devices represent the largest class of counterfeit devices and are becoming more rampant. Therefore, it is often necessary to test whether a device is counterfeit before employing it in a new system. Current methods for evaluating the genuine nature of devices are frequently destructive, allowing for only small sample testing within lots. Other methods require complex external equipment and cannot be readily deployed throughout the supply chain. Graf Research Corporation has developed a methodology for using telemetry bitstreams to characterize an FPGA device and subsequently classify whether a device is a repackaged counterfeit via statistical and machine learning models. The new method utilizes minimal external equipment, is non-destructive, and can be employed at any point throughout the supply chain.
GOMACTech 2024 Poster Session
March 21, 2024, 10:30-12:00 PM
The Role of EDA in FPGA Assurance Best Practices
Margaret Winslow, Jonathan Graf, Whitney Batchelor, Scott Harper, Kevin Paar, Ali Asgar Sohanghpurwala
Abstract: Developing assured microelectronics requires coordination throughout the lifecycle of the device to ensure that necessary assurance policy, guidance, and/or best practices are met. Assurance practices recommended by the recently-published DoD Microelectronics: FPGA Level of Assurance 1 Best Practices and related guidance for higher levels of assurance (LoAs) can be categorized such that programs can delegate assurance tasks across personnel within a program. A significant portion of assurance practices remain dependent on the actions of the development team, however. This paper explores which of the assurance practices that fall to the development team are automatable using Electronic Design Automation (EDA) tools and which involve more manual interventions and practices, highlighting specific tools of interest to the FPGA assurance community. This work concludes that all assurance tasks left to the development team are accelerable with traditional and emerging EDA tools, making compliance with LoA best practices a tractable challenge.