At the upcoming AMD Security Working Group, Graf Research will share our latest contributions to advancing FPGA security and assurance.
Our joint presentation with AMD, “Isolation Design Flow / Verifying Isolation at the Bitstream Level”, will demonstrate how engineers can design with confidence by validating critical isolation properties in the FPGA bitstream. We will also introduce the Forge Security Lifecycle Manager, a new tool that streamlines assurance throughout the hardware development process.
Beyond our technical sessions, we are excited to connect with partners and colleagues during Partner Night, where we’ll discuss the broader Enverite suite and its role in strengthening the FPGA security ecosystem. Don’t miss this opportunity to engaging in meaningful collaboration with the wider security and semiconductor community.
Longmont, CO, from October 14 – 15, 2025
Washington, D.C., from November 5 – 6, 2025
Munich, Germany, from December 9 – 10, 2025
For more information, visit https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/design-security.html#security-working-group