Graf Research is proud to announce that Dr. Ali Asgar Sohanghpurwala will present at IEEE SecDev 2025 on “PV-Bit: Private Verification of FPGA Bitstreams Via Bitstream Equivalence Checking.”
This talk will explore the theory and practice of private verification, showing how PV-Bit enables organizations to confirm bitstream equivalence without exposing sensitive design details. Dr. Sohanghpurwala will detail how we evaluated PV-Bit against an open-source design set for both false positives in unmodified designs and accurate detection for designs with fault injections.
PV-Bit represents a key advance in protecting both intellectual property and mission-critical systems. We look forward to sharing our latest research with the SecDev community and advancing the state of practice in secure hardware design.
PV-Bit: Private Verification of FPGA Bitstreams Via Bitstream Equivalence Checking
Ali Asgar Sohanghpurwala, Daniel Gibson, Scott Harper, Jonathan Graf, Timothy Dunham
Established FPGA design verification flows utilize sophisticated methods to provide assurance for microelectronic designs deployed on FPGA based systems, but they lack visibility into the vendor proprietary configuration bitstream format. This means the assurances they provide only extend as far as the post place and route simulation netlist, leaving a verification gap where errors or malicious modifications could be introduced during the bitstream generation process. Here, we discuss and evaluate the operation and efficacy of PV-Bit as a tool that can address this gap via Bitstream Equivalence Checking: proving physical (and thus functional) equivalence between the bitstream and a verified, trusted netlist. PV-Bit uniquely performs this check without exposing private Intellectual Property included in the bitstream.