Graf Research is proud to sponsor and exhibit at the 45th Digital Avionics Systems Conference (DASC), taking place September 13–17, 2026, in Orlando, Florida. This year’s conference focuses on Safe and Secure Digital Avionics in the Age of AI, making it a great opportunity to discuss our research and Enverité capabilities for safety and assurance in FPGA-based avionics systems. Stop by the Graf Research booth to meet the team and learn more.
We are also excited to announce that our paper, “Accelerating FPGA-Based Avionics System Recertification with Delta Verification Methodologies and Bitstream-Level Verification of Physical Isolation,” received a Best of Session Award. Dr. Ali Asgar Sohanghpurwala will present the paper on Tuesday, September 15th from 2:00–2:30 PM during the Tools for Data Management and Development session. The presentation will highlight our work applying delta verification and bitstream-level verification to FPGA-based avionics systems.
Learn more about DASC 2026 and view the conference program on the DASC website.
Accelerating FPGA-Based Avionics System Recertification with Delta Verification Methodologies and Bitstream-Level Verification of Physical Isolation
Ali Asgar Sohanghpurwala, Jonathan Graf, Evan Drinkert, Scott Harper, Meg Winslow
Field programmable gate arrays (FPGAs) offer a unique balance of performance, efficiency, and flexibility that make them uniquely suited for use in digital avionics. Avionics systems often support safety and security critical functions alongside non-critical functions. Ensuring the critical functions are implemented with sufficient fault tolerance is emphasized by standards bodies with stringent certification regimes. FPGA vendors aid in compliance by providing isolation design flows that enable containment of faults to specific hardware functions. Here we present how PV-Bit further assures such designs by verifying that isolation properties verified at the netlist-level are preserved in the bitstream via Bitstream Equivalence Checking (BEC). Furthermore, we present how this can be combined with the delta verification concept to narrow the recertification scope for certain FPGA design changes.