GOMAC 2019: “Introducing a Trust Metric Foundation and Deriving Trust-for-Buck”

Graf Research Corporation will be returning to GOMAC, this time in Albuquerque, New Mexico. In addition to marveling at the ridges of the Sandia mountains and the wine-colored sunsets of New Mexico, we’ll be presenting our paper, “Introducing a Trust Metric Foundation and Deriving Trust-for-Buck.” Paper contributors include Scott Harper, Jonathan Graf, Whitney Batchelor, Tim Dunham, and Peter Athanas. If you’re going to GOMAC, come out and say hello to us!

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Hardware Trojan Detection using Xilinx Vivado

Scott Harper, Jonathan Graf, Whitney Batchelor, Tim Dunham, Peter Athanas

Abstract: This study defines a flexible quantitative metric for measuring trust-related aspects across a broad range of domains and a means of using that foundation to derive domain-specific measurements. A Trust Basis Metric is described here along with examples that build on its foundation to measure assurances and identify cost-effective trust-enhancing investments. Our primary motivation in performing this study was to quantitatively determine the best increase in trust per dollar (Trust-for-Buck) when investing in current device manufacture and distribution flows for microelectronic components.

Graf Research at IEEE HOST (and TAME and WISE)

Graf Research will be at the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) as well as the co-located workshops the Trusted and Assured MicroElectronics Forum (TAME) and Women in Hardware and Systems Security (WISE).   Please say hello to Jonathan Graf, who will be a poster session chair and judge at HOST and a panelist in the TAME forum, and Whitney Batchelor, who will be a poster judge at WISE.  See you there!

Graf Research Awarded SBIR: "GR-TDM: A Framework for Design Space Exploration of Hardware Trojan Detection and Mitigation Tradeoffs"

Graf Research is pleased to announce the kickoff of a new DARPA project entitled "GR-TDM: A Framework for Design Space Exploration of Hardware Trojan Detection and Mitigation Tradeoffs." 

Title III Trusted FPGA Briefing at NDIA FPGA Assurance Workshop

Jonathan Graf and Scott Harper will be attending the NDIA FPGA Assurance Workshop on February 27-28.  Our sponsors will be briefing on our research from the DPA Title III Trusted FPGA program.  Come on out, learn about our research, and chat with Scott and Jon!

Graf Research Awarded Phase 2 SBIR: "Optimal Strategies for Cloud-Based Trust Assessment"

Graf Research has been awarded a Phase 2 SBIR to continue our work on Optimal Strategies for Cloud-Based Trust Assessment.

Graf Research Awarded Contract to Interface OpTrust Tools

Graf Research has been awarded a contract to create interfaces between our OpTrust software, which creates game-theory-based prescriptions for optimal hardware Trojan detection, and a prime contractor's custom electronic design automation tools. 

SEE/MAPLD 2017 Invited Lecture: "Optimizing Forward Design Trust for FPGAs"

Jonathan Graf will present an invited lecture on "Optimizing Forward Design Trust for FPGAs" at the 2017 Single Event Effects Symposium / Military and Aerospace Programmable Logic Devices Workshop in San Diego on May 25.  Come on out and see us!

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Optimizing Forward Design Trust for FPGAs

Jonathan Graf

Abstract: Graf Research Corporation is developing a workflow to enable optimal forward design trust for Field Programmable Gate Arrays.  This flow is enabled by a blend of commercial EDA software, Graf Research specialized tools and techniques, and, as needed, custom trust analysis tools and techniques.  Custom tools include PV-Bit, which bridges the current gap between a trusted gate level netlist and the FPGA bitstream, bringing trust all the way into the bitstream.  To develop a trusted gate-level netlist, other trust analysis techniques must have preceded the use of PV-Bit.  The Graf Research contribution during synthesis, map, place, and route steps, is a tool called OpTrust, which uses a game theoretic decision engine to prescribe the optimal set of tests for the trust analysis of a design based on current threat data, the criticality of the design, and the availability of commercial verification or custom hardware Trojan detection methods.  Another element of trusted design is trusting the 3rd-Party IP cores present in the design.  The end goal of this assessment flow is to put the trust analysis of FPGA designs within the reach of the FPGA developer.  That is, we wish to ensure that the developer might perform the trust analysis themselves, pushing trust forward as each step in the design process is completed, concluding with a trusted bitstream.

Graf Research Awarded BAA: DPA Title III Trusted FPGAs

Graf Research has been awarded a Phase 0 BAA research project entitled DPA Title III Trusted FPGAs.  

Brief Program Summary: The Department of Defense (DoD) and Intelligence Community (IC) have identified Field Programmable Gate Arrays (FPGAs) as a critical enabling technology across a wide variety of present and future systems. Advanced, commercially available FPGAs do not meet DoD's requirements for Trusted Systems as they are manufactured in un-Trusted fabrication facilities, primarily off-shore, and are considered vulnerable to tampering and insertion of malicious software and/or hardware. This program seeks to improve the security posture and reduce the risk associated with FPGA technology by addressing security concerns in the design, development, fabrication and supply lifecycle of FPGA devices. The purpose of this study is to conduct an analysis and develop an approach to ensure the availability of advanced “Trusted” and space qualified re-programmable FPGAs technology to support DoD/IC applications including satellite and strategic missile systems. “Trust” is defined as assurance of the integrity and availability of a product wherein that product will reliably operate as intentionally designed and not contain any malicious hardware and/or software that will compromise the intended application; e.g., exfiltration of sensitive data, etc. Efforts envisioned during this Phase 0 study include: analysis of current FPGA manufacturing capabilities; analysis of future technical capabilities needed to meet the needs of the FPGA market (USG and commercial); creation of a draft technical plan and schedule to establish a Trusted source for space qualified FPGA devices, to include (non-binding) high-level cost projections, to establish quantitative “Trust” criteria for FPGAs; identification and analysis of the markets for FPGAs; and identification of business strategies to ensure long term success in the Trusted and space qualified FPGA market.

Invited Talk at NDIA FPGA Assurance Workshop

Jonathan Graf will be giving an invited talk, entitled "A Few Thoughts about FPGA Trust," and leading a working group brainstorming session at the 2017 NDIA FPGA Assurance Workshop on March 1-2.  Be sure to come out to attend this stimulating event!

Graf Research Awarded SBIR: "Optimal Strategies for Cloud-Based Trust Assessment"

Graf Research has been awarded a Phase 1 SBIR to research and develop optimal strategies for cloud-based trust assessment. We anticipate creating not only a novel cloud architecture that can facilitate the use of many of the DARPA-sponsored custom microelectronics trust software tools but also a unique, cloud-hosted software product OpTrust-C which will devise optimal strategies for the proper implementation of defensive measures.

IEEE NAECON 2016: "System-Level Adversary Attack Surface Modeling for Microelectronics Trust"

Continuing our publication of the applications of Game Theory to various levels of trust assessment, we discuss system-level applications in our IEEE NAECON 2016 paper. Come on out and see our presentation!

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Towards System-Level Adversary Attack Surface Modeling for Microelectronics Trust
Jonathan Graf

Abstract: Models of trust for microelectronic systems are difficult to create due to the large variety of adversarial strategies available. Building on previous work, we present a new adversary model that considers the large heterogeneous attack surface that is realistically available on a diverse microelectronic system. We also present an expanded game theoretic model that permits reasoning about optimal adversarial and defensive strategies across this varied attack surface.

Invited Lecture for the Potomac Institute for Policy Studies

Jonathan Graf will be presenting an invited lecture entitled "FPGA Trust: Threats, Methods, Metrics, and Optimization" to the Hardware Security Symposium at the Potomac Institute for Policy Studies on May 2, 2016.  

GOMAC 2016: "Optimal Hardware Trojan Detection through Security Economics and Game Theory"

We're going to GOMAC this year to present our paper, "Toward Optimal Hardware Trojan Detection through Security Economics and Game Theory."  Come on out to see us!

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Toward Optimal Hardware Trojan Detection through Security Economics and Game Theory

Jonathan Graf

Abstract: We present a security economic model that informs the optimal selection of hardware Trojan detection strategies.  Our model accurately represents the economics and efficacy of available verification and Trojan detection methods and accounts for the varieties of available hardware Trojans.  Paired with game theoretic analysis, this model informs ASIC/FPGA designers and associated policy makers of optimal defensive strategies.