News and Events
This week, Ali Asgar Sohangpurwala of Graf Research will present the "GR-TDM: A Framework for Design Space Exploration of Hardware Trojan Detection and Mitigation Tradeoffs" project in Los Angeles at DARPA's "Obfuscated Manufacturing for GPS (OMG)" kickoff meeting. If you are attending, please say hello!
Graf Research will be at the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) as well as the co-located workshops the Trusted and Assured MicroElectronics Forum (TAME) and Women in Hardware and Systems Security (WISE). Please say hello to Jonathan Graf, who will be a poster session chair and judge at HOST and a panelist in the TAME forum, and Whitney Batchelor, who will be a poster judge at WISE. See you there!
Graf Research will continue our work developing solutions that blend the needs of Mission Assurance with Cyber Physical Systems security under an additional $1M of Army/OSD funding. We are proud to have Georgia Tech as a partner on this work, and we are happy to be funding both faculty and graduate student research positions through this collaboration.
Graf Research is pleased to announce the kickoff of a new DARPA project entitled "GR-TDM: A Framework for Design Space Exploration of Hardware Trojan Detection and Mitigation Tradeoffs."
After two years as a Xilinx Alliance Program Associate, Graf Research has upgraded our status in the Xilinx Alliance Program to the "Member" level! Xilinx examined our quality, business, and technical practices through a self-audit we submitted in order to meet the corporate requirements for membership. Xilinx further trained our staff to be certified as proficient and knowledgeable in the latest Xilinx technologies.
As we continue to collaborate with Xilinx and make use of their technologies, we are pleased to take this step in our relationship.
Scott Harper from Graf Research will be attending GOMAC 2018 in Miami from March 12-15. Our very own Scott Harper and Tim Dunham are co-authors on "Malicious Trigger Discovery in FPGA Firmware." Make sure to say hello to Scott!
Jonathan Graf and Scott Harper will be attending the NDIA FPGA Assurance Workshop on February 27-28. Our sponsors will be briefing on our research from the DPA Title III Trusted FPGA program. Come on out, learn about our research, and chat with Scott and Jon!
Graf Research has been awarded a multi-year contract to research and develop signal processing algorithms, software defined radio solutions, and FPGA implementations.
Graf Research has been awarded a Phase 2 SBIR to continue our work on Optimal Strategies for Cloud-Based Trust Assessment.
Graf Research has been awarded an SBIR to produce one or more ASIC and FPGA hardware 3rd-Party IP (3PIP) assessment techniques, a set of technologies we collectively refer to as GR-3PIP. The techniques must accomplish the goal of establishing trust in the 3PIP under test, but we apply additional requirements. We require that the techniques (1) do not add significant cost to the core, (2) do not require extensive time to apply, and (3) do not require extensive verification or reverse engineering expertise to use.
Graf Research has been awarded a Phase 2 SBIR to continue our work on Irrefutable Tamper Logging.
Graf Research Corporation is going to XSWG! We have been invited to give the lecture “A Cryptographically Secure Immutable Memory for Irrefutable Tamper Logging” at both groups: Longmont, Colorado (Oct 17-19) and Herndon, Virginia (Nov 7-9). Contributors to the lecture include Jonathan Graf, Ali Asgar Sohanghpurwala, Matt French, and Dr. Andrew Schmidt from USC-ISI. Register for the conference and come see us!
Graf Research has been awarded a contract to put our OpTrust tools in a high-security cloud environment to provide trust guidance to developers.
Jonathan Graf will be presenting an "Overview of Game Theoretic Analysis Work" at the Air Force Trusted & Assured Microelectronics Symposium at Wright-Patterson Air Force Base on August 30. Come on out and hear our talk!
Graf Research has been awarded a contract to create interfaces between our OpTrust software, which creates game-theory-based prescriptions for optimal hardware Trojan detection, and a prime contractor's custom electronic design automation tools.
We’ve moved to a new office in Blacksburg! We are busy ordering furniture, office flair, and other accommodations. This will be a comfortable space where our team members can come together and collaborate effectively.
Full of potential!
A shot of the exterior.
Take a look at our awesome new sign. It even lights up in the dark!
Graf Research and Georgia Tech are publishing and presenting our research on “Formal Enforcement of Mission Assurance Properties in Cyber-Physical Systems” at IEEE NAECON 2017. Come out and see our presentation!
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Formal Enforcement of Mission Assurance Properties in Cyber-Physical Systems
Scott Harper, Jonathan Graf, Michael A. Capone, Justin Eng, Michael Farrell, Lee W. Lerner
Abstract: Cyber-Physical Systems improve efficiency, accuracy, and access in systems ranging from household appliances to power stations to airplanes. They also bring new risks at the intersection of physical, information, and mission assurance. This paper presents CP-SMARTS, a framework providing a means for propagating CPS assurances from planning to deployment.
Jonathan Graf will present an invited lecture on "Optimizing Forward Design Trust for FPGAs" at the 2017 Single Event Effects Symposium / Military and Aerospace Programmable Logic Devices Workshop in San Diego on May 25. Come on out and see us!
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Optimizing Forward Design Trust for FPGAs
Jonathan Graf
Abstract: Graf Research Corporation is developing a workflow to enable optimal forward design trust for Field Programmable Gate Arrays. This flow is enabled by a blend of commercial EDA software, Graf Research specialized tools and techniques, and, as needed, custom trust analysis tools and techniques. Custom tools include PV-Bit, which bridges the current gap between a trusted gate level netlist and the FPGA bitstream, bringing trust all the way into the bitstream. To develop a trusted gate-level netlist, other trust analysis techniques must have preceded the use of PV-Bit. The Graf Research contribution during synthesis, map, place, and route steps, is a tool called OpTrust, which uses a game theoretic decision engine to prescribe the optimal set of tests for the trust analysis of a design based on current threat data, the criticality of the design, and the availability of commercial verification or custom hardware Trojan detection methods. Another element of trusted design is trusting the 3rd-Party IP cores present in the design. The end goal of this assessment flow is to put the trust analysis of FPGA designs within the reach of the FPGA developer. That is, we wish to ensure that the developer might perform the trust analysis themselves, pushing trust forward as each step in the design process is completed, concluding with a trusted bitstream.
Graf Research and the University of Southern California's Information Sciences Institute will publish our work on “Irrefutable Tamper Logging through FPGA Key Management” at the 2017 DoD Anti-Tamper Conference. Co-authors include Jonathan Graf and Ali Asgar Sohanghpurwala from Graf Research and Matthew French and Dr. Andrew Schmidt from USC-ISI.
Graf Research has been awarded a Phase 0 BAA research project entitled DPA Title III Trusted FPGAs.
Brief Program Summary: The Department of Defense (DoD) and Intelligence Community (IC) have identified Field Programmable Gate Arrays (FPGAs) as a critical enabling technology across a wide variety of present and future systems. Advanced, commercially available FPGAs do not meet DoD's requirements for Trusted Systems as they are manufactured in un-Trusted fabrication facilities, primarily off-shore, and are considered vulnerable to tampering and insertion of malicious software and/or hardware. This program seeks to improve the security posture and reduce the risk associated with FPGA technology by addressing security concerns in the design, development, fabrication and supply lifecycle of FPGA devices. The purpose of this study is to conduct an analysis and develop an approach to ensure the availability of advanced “Trusted” and space qualified re-programmable FPGAs technology to support DoD/IC applications including satellite and strategic missile systems. “Trust” is defined as assurance of the integrity and availability of a product wherein that product will reliably operate as intentionally designed and not contain any malicious hardware and/or software that will compromise the intended application; e.g., exfiltration of sensitive data, etc. Efforts envisioned during this Phase 0 study include: analysis of current FPGA manufacturing capabilities; analysis of future technical capabilities needed to meet the needs of the FPGA market (USG and commercial); creation of a draft technical plan and schedule to establish a Trusted source for space qualified FPGA devices, to include (non-binding) high-level cost projections, to establish quantitative “Trust” criteria for FPGAs; identification and analysis of the markets for FPGAs; and identification of business strategies to ensure long term success in the Trusted and space qualified FPGA market.
