Graf Research will be participating in the 2026 DoD Anti-Tamper Conference from April 21–23 in Laurel, Maryland. For more information about the event, click here.
Throughout the event, Graf Research will have two research presentations, a poster, and a booth showcasing Enverité EDA software for FPGA assurance and verification. Enverité supports the verification of FPGA designs in both safety and security critical applications, helping organizations strengthen trust in complex systems.
Whitney Batchelor will be presenting her paper "Accelerating Netlist Reverse Engineering with Agentic AI."
Kevin Paar will be presenting his paper "Anti-Tamper Implementation: A Framework for Complete Zeroization of AMD Versal SoC Based Systems."
Scott Harper will be presenting the poster "Forge: A Security Lifecycle Manager for FPGAs."
Members of the Enverité team will be available at our booth and would love to connect with researchers, engineers, industry practitioners, and everyone in-between. If you are attending AT, please stop by our booth and learn more about how Enverité supports FPGA design assurance workflows.
Interested in our research or the capabilities of our Enverité software? Please reach out at info@enverite.com with any questions, we would love to chat!
We look forward to engaging with the Anti-Tamper community and sharing further updates in the months ahead.